Reconfigurable processor for executing successive function seque

Reconfigurable processor with alternately interconnected...

Reconfigurable semantic processor

Reconfigurable single instruction multiple data array

Reconfigurable VLIW processor

Reconfiguration of execution path upon verification of...

Recorder buffer and a method for allocating a fixed amount of st

Recovering a subordinate strand from a branch misprediction...

Recovery from writeback stage event signal or micro-branch...

Recovery of global history vector in the event of a...

Recursively accessing a branch target address cache using a...

Recycling long multi-operand instructions

Reduced instruction fetch latency in a system including a...

Reduced instruction set computer architecture with...

Reduced overhead address mode change management in a...

Reduced power parallel processor apparatus

Reduced size storage apparatus for storing cache-line-related da

Reducing branch prediction interference of opposite well...

Reducing data dependent conflicts by converting single precision

Reducing data hazards in pipelined processors to provide...