Reduced instruction set computer architecture with...

Details Reduced instruction set computer architecture with... Reduced instruction set computer architecture with...

2006-09-26

2006-09-26

Chan, Eddie (Department: 2183)

Electrical computers and digital processing systems: processing

Processing architecture

Microprocessor or multichip or multimodule processor having...

C712S223000, C712S224000, C712S300000, C714S801000

Reexamination Certificate

active

07114055

ABSTRACT:
A reduced instruction set computer architecture implemented on a field programmable gate array includes a parallel bit shifter capable of reversible shifts and bit reversals, a Reed-Muller Boolean unit coupled to the parallel bit shifter and an immediate instruction function using a half-word literal field in an instruction word that impacts a whole word logically through a combination of modes that variously manipulates the distribution of a set of literal bits of the half-word literal field across the instruction word.

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