Recycling long multi-operand instructions

Electrical computers and digital processing systems: processing – Processing control

Reexamination Certificate

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Details

C712S219000

Reexamination Certificate

active

07962726

ABSTRACT:
A pipelined microprocessor configured for long operand instructions is disclosed. The microprocessor includes a memory unit and a load-store unit. The load store unit is coupled to the memory unit and includes a data formatter receiving information from the memory unit and including an operand selector and a shift register portion. The microprocessor also includes an execution unit coupled to the load-store unit and receiving operand information there from. The execution unit includes output latches coupled to a storage location within the execution unit for storing output information from the execution unit.

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patent: 6047370 (2000-04-01), Grochowski
patent: 6385715 (2002-05-01), Merchant et al.
patent: 2004/0139299 (2004-07-01), Busaba et al.
patent: 2004/0230773 (2004-11-01), Busaba et al.
“IBM® z/Architecture Principles of Operation”, Publication No. SA22-7832-05, 6th Edition, Apr. 2007. 1,215 pages separated into 4 electronic attachments.

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