Reducing data hazards in pipelined processors to provide...

Details Reducing data hazards in pipelined processors to provide... Reducing data hazards in pipelined processors to provide...

2007-02-26

2010-06-08

Li, Aimee J (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

C712S213000, C712S219000

Reexamination Certificate

active

07734899

ABSTRACT:
A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of instructions to operate concurrently on multiple pieces of data in multiple passes. One subset of instructions operates on one piece of data while different subsets of instructions operate concurrently on different pieces of data. A validity pipeline tracks the priming and draining of the pipeline processor to ensure that only valid data is written to registers or memory. Pass-dependent addressing is provided to correctly address registers and memory for different pieces of data.

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Jacobson, Hans M.; Kudva, Prabhakar N.; Bose, Pradip; Cook, Peter W.; Schuster, Stanley E.; Mercer, Eric G.; and Myers, Chris J., “Synchronous Interlocked Pipelines”, Eigth International Symposium on Asynchronous Circuits and Systems, 2002, Proceedings, © Apr. 8-11, 2002, IEEE. pp. 3-12.
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