Reconfigurable single instruction multiple data array

Details Reconfigurable single instruction multiple data array Reconfigurable single instruction multiple data array

2005-03-08

2005-03-08

Tsai, Henry W. H. (Department: 2183)

Electrical computers and digital processing systems: processing

Processing architecture

Array processor

C712S022000

Reexamination Certificate

active

06865661

ABSTRACT:
A reconfigurable single instruction multiple data array includes a plurality of processing cells; a serial data bus with at least one line dedicated to each cell; each cell including an identification number for uniquely identifying each cell and its dedicated line and a communication port including at least one parallel to serial transmitter circuit in each cell for broadcasting its cell's output data over its dedicated line; at least one serial to parallel receiver circuit in each cell; each cell responsive to the identification number and a common command word to generate a local configuration command designating a pre-selected broadcasting cell and a configuration register associated with each receiver circuit and responsive to the local configuration command to condition its receiver's circuit to receive serial input data broadcast from the pre-selected cell's dedicated line.

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