Processor having multiple program counters and trace buffers...
Processor having operating instruction which uses operation...
Processor having replay architecture with fast and slow...
Processor having selectable exception handling modes
Processor having selective branch prediction
Processor having vector processing capability and method for...
Processor including a combined parallel debug and trace port...
Processor including a plurality of computing devices
Processor including a register file and method for computing...
Processor including efficient fetch mechanism for L0 and L1...
Processor including efficient fetch mechanism for L0 and L1...
Processor including fallback branch prediction mechanism for...
Processor including replay queue to break livelocks
Processor instruction control mechanism capable of decoding regi
Processor instruction including option bits encoding which...
Processor instruction pipeline with error detection scheme
Processor instruction with repeated execution code
Processor instruction with repeated execution code
Processor livelock recovery by gradual stalling of...
Processor lock