Electrical computers and digital processing systems: processing – Processing control – Specialized instruction processing in support of testing,...
Reexamination Certificate
1997-12-17
2001-01-16
Follansbee, John A. (Department: 2783)
Electrical computers and digital processing systems: processing
Processing control
Specialized instruction processing in support of testing,...
C712S032000, C712S039000, C712S040000, C714S744000, C714S789000, C714S012000, C714S034000
Reexamination Certificate
active
06175914
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to debug support in microprocessors, and more particularly to combining a parallel debug port and a trace port.
2. Description of the Related Art
The growth in software complexity, coupled with increasing processor clock speeds, has placed an increasing burden on application software developers. The cost of developing and debugging new software products is now a significant factor in processor selection. A processor's failure to adequately facilitate software debug results in longer customer development times and reduces the processor's attractiveness for use within industry. The need to provide software debug support is particularly acute within the embedded products industry, where specialized on-chip circuitry is often combined with a processor core.
In addition to the software engineer, other parties are also affected by debug tool configuration. These parties include: the “trace” algorithm developer who must search through captured software trace data that reflects instruction execution flow in a processor; the in-circuit emulator developer who deals with problems of signal synchronization, clock frequency and trace bandwidth; and the processor manufacturer who does not want a solution that results in increased processor cost or design and development complexity.
With desktop systems, complex multitasking operating systems are currently available to support debugging. However, the initial task of getting these operating systems running reliably often requires special development equipment. While not the standard in the desktop environment, the use of such equipment is often the approach taken within the embedded industry. Logic analyzers, read-only memory (ROM) emulators and in-circuit emulators (ICE) are frequently employed. In-circuit emulators do provide certain advantages over other debug environments, offering complete control and visibility over memory and register contents, as well as overlay and trace memory in case system memory is insufficient. Use of traditional in-circuit emulators, which involves interfacing a custom emulator back-end with a processor socket to allow communication between emulation equipment and the target system, is becoming increasingly difficult and expensive in today's age of exotic packages and shrinking product life cycles.
Assuming full-function in-circuit emulation is required, there are a few known processor manufacturing techniques able to offer the required support for emulation equipment. Most processors intended for personal computer (PC) systems utilize a multiplexed approach in which existing pins are multiplexed for use in software debug. This approach is not particularly desirable in the embedded industry, where it is more difficult to overload pin functionality.
Other more advanced processors multiplex debug pins in time. In such processors, the address bus is used to report software trace information during a BTA-(Branch Target Address) cycle. The BTA-cycle, however, must be stolen from the regular bus operation. In debug environments where branch activity is high and cache hit rates are low, it becomes impossible to hide the BTA-cycles. The resulting conflict over access to the address bus necessitates processor “throttle back” to prevent loss of instruction trace information. In the communications industry, for example, software typically makes extensive use of branching and suffers poor cache utilization, often resulting in 20% throttle back or more. This amount of throttling is unacceptable amount for embedded products which must accommodate real-time constraints.
In another approach, a second “trace” or “slave” processor is combined with the main processor, with the two processors operating in-step. Only the main processor is required to fetch instructions. The second, slave processor is used to monitor the fetched instructions on the data bus and keeps its internal state in synchronization with the main processor. The address bus of the slave processor functions to provide trace information. After power-up, via a JTAG (Joint Test Action Group) input, the second processor is switched into a slave mode of operation. Free from the need to fetch instructions, its address bus and other pins provide the necessary trace information.
In yet another approach (the “Background Debug Mode” by Motorola, Inc.) limited on-chip debug circuitry is provided for basic run control. Through a dedicated serial link requiring additional pins, this approach allows a debugger to start and stop the target system and apply basic code breakpoints by inserting special instructions in system memory. Once halted, special commands are used to inspect memory variables and register contents. This serial link, however, does not provide a high performance trace or debug support. Thus, for example, there is not high speed access to system memory.
Another existing approach involves building debug support into every processor, but only bonding-out the necessary signal pins in a limited number of packages. These specially packaged versions of the processor are used during debug and replaced with the smaller package for final production. This bond-out approach suffers from the need to support additional bond pad sites in all fabricated devices. This can be a burden in small packages and pad limited designs, particularly if a substantial number of extra pins are required by the debug support variant. Additionally, the debug capability of the specially packaged processors is unavailable in typical processor-based production systems.
Thus, there is a need to address a variety of limitations in present debugging approaches including the need to provide not only low speed solutions via a serial port, but also to provide high performance trace and debug solutions without paying too high a penalty in terms of bond pad sites.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides trace information over a communication port that is operable both as a trace port and as a parallel debug port. The trace port provides trace information indicating instruction execution flow in the processor core. The parallel debug port provides for transmission of debug information between a debug host controller and the processor. The operation of the communication port as a trace port and as a parallel debug port is mutually exclusive. The parallel debug port and the trace port physically share a majority of input/output terminals of the communication port. Bus request and grant signals are provided between the parallel debug port and a debug host controller to ensure that collisions do not occur between use by the trace port and the debug host controller. A separate serial debug port is also provided which can be used to enable the parallel debug port.
Accordingly, one embodiment of the invention provides a processor having a processor core and a parallel trace port providing trace information indicating instruction execution flow in the processor core. A parallel debug port on the processor provides for sending and receiving debug commands and data from/to a debug host controller and the processor. The operation of the trace port and the parallel debug port are mutually exclusive.
In another embodiment, the invention provides a method of operating a processor which includes a processor core and a communication port which is selectably operable as one of a trace port and a parallel debug port. The method includes operating the communication port as a trace port to provide trace information over the trace port and then stopping operation of the processor core. The communication port is then enabled to operate as the parallel debug port by writing to a control register on the processor. Once the parallel debug port is enabled, it can be used to write debug commands and data to the processor.
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patent: 4462077 (1984-07-01), York
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Advanced Micro Devices , Inc.
Follansbee John A.
Nguyen Dzung C.
Zagorin O'Brien & Graham LLP
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