Processor instruction pipeline with error detection scheme

Details Processor instruction pipeline with error detection scheme Processor instruction pipeline with error detection scheme

1999-07-23

2002-09-24

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Specialized instruction processing in support of testing,...

C712S231000

Reexamination Certificate

active

06457119

ABSTRACT:

BACKGROUND
1. Field
This disclosure relates to a processor instruction pipeline. More particularly, a pipeline for processing microcode or machine-readable instructions with an error-detection scheme.
2. Background Information
As is well-known, digital electronic circuitry may experience soft errors. Soft errors are typically the result of external random events, such as radiation. These external random events may cause a digital logic value to switch from its intended value, e.g. from logic ‘1’ to logic ‘0’. As is also well-known, soft errors are transient in nature. More particularly, after the effects of a soft error are corrected, digital electronic components will typically function as expected.
The occurrence of a soft error in a processor instruction pipeline may corrupt one or more microcode or machine readable instructions by resulting in the switching of logic levels in one or more instructions to an opposite state from the intended state. Microcode or machine readable instructions are executed by a processor in carrying out its intended operations. Corrupted microcode or machine readable instructions, in turn, may result in a system in which a processor is employed halting or behaving in an undesired manner. A need, therefore, exists for a scheme to handle the occurrence of corrupted microcode or machine readable instructions in a processor instruction pipeline that reduces the effects of these corrupted instructions on processor operation.
SUMMARY
Briefly, in accordance with one embodiment of the invention, a processor includes: a multiple unit instruction pipeline. An instruction pipeline includes a microcode source. The microcode source includes the capability of detecting the occurrence of at least one corrupted microcode instruction. The microcode source is also capable of signaling the occurrence of at least one corrupted microcode instruction to at least one other instruction pipeline unit.
Briefly, in accordance with another embodiment of the invention, a method of executing microcode instructions includes the following. The existence of at least one corrupted microcode instruction is detected and the occurrence of at least one corrupted microcode instruction is signaled.
Briefly, in accordance with one more embodiment of the invention, a system includes: a processor with a microcode source capable of detecting the occurrence of at least one corrupted microcode instruction and signaling the occurrence of at least one corrupted microcode instruction to at least one other instruction pipeline unit. The system employing the processor further includes main memory, a video card, a system bus, and bulk storage capability.


REFERENCES:
patent: 5150469 (1992-09-01), Jouppi
patent: 5269017 (1993-12-01), Hayden
patent: 5446849 (1995-08-01), Minagawa et al.
patent: 5629950 (1997-05-01), Godiwala
patent: 5740391 (1998-04-01), Hunt
patent: 5799165 (1998-08-01), Favor et al.
patent: 5867699 (1999-02-01), Kuslak
patent: 5870601 (1999-02-01), Getzlaff et al.
patent: 5881078 (1999-03-01), Hanawa
patent: 5961655 (1999-10-01), Johnson
patent: 6055630 (2000-04-01), D'Sa
patent: 6079014 (2000-06-01), Papworth
U.S. patent application Ser. No. 08/956,375, Krick et al., filed Oct. 23, 1997.
Eric Rotenberg, Steve Bennett, James E. Smith, “Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching”, Published in the Proceedings of the 29th Annual International Symposium on Microarchitecture, Dec. 2-4, 1996, IEEE, 12 pages.

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