Processor instruction with repeated execution code

Details Processor instruction with repeated execution code Processor instruction with repeated execution code

2008-03-18

2008-03-18

Kindred, Alford (Department: 2181)

Electrical computers and digital processing systems: processing

Processing control

Branching

C712S208000

Reexamination Certificate

active

10857964

ABSTRACT:
The present invention relates to a design of a computer system that processes instructions with a specific operation code causing the processor to execute a certain operation twice and a method for running such computer system in a time and register space saving manner. A method is provided for executing at least one computer instruction which defines at least a first source operand and an operation to be carried out on the operand, the instruction containing at least one address field of a predetermined bit length and at least one repeated execution bit related to the first operand. The method includes accessing the first source operand; accessing the repeated execution bit and deriving from that repeated execution bit a repeated execution code defining a repeated execution condition; and selectively carrying out the operation defined in the instruction once, twice or more times in dependence of the repeated execution code. This method has the advantageous effect that in case an instruction shall be performed twice or more times, no separate or additional special instruction is necessary, thereby register space and the time for processing separate or additional logical instructions is saved.

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“Advanced Computer Architectures”; Sima et al; 1997; Addison-Wesley; p. 89-95, 175-179.

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