Processor instruction control mechanism capable of decoding regi

Details Processor instruction control mechanism capable of decoding regi Processor instruction control mechanism capable of decoding regi

1997-12-19

1999-08-17

Treat, William M.

Electrical computers and digital processing systems: processing

Instruction decoding

Decoding instruction to accommodate plural instruction...

712229, G06F 930

Patent

active

059387599

ABSTRACT:
An instruction control mechanism, for processors, capable of decoding a register instruction and an immediate instruction with a simple configuration, is disclosed. The instruction control mechanism decodes and executes an instruction set including an instruction code having an instruction field, a first field containing the description of the name of the register to be processed and a second field containing the description of the name of another register or an immediate address. A register instruction code containing the description of another register to be processed in the second field has an instruction field of a specific value, and contains the description of a second instruction field in the portion other than the second field containing another register to be processed. An immediate instruction code containing the description of an immediate address in the second field has an instruction field containing the description of other than the specific value. At least part of the immediate instruction code and at least part of an immediate-like register instruction code for performing the same processing except that the immediate address and another register to be processed are used, are assigned the same value in the first instruction field and the second instruction field.

REFERENCES:
patent: 3781823 (1973-12-01), Senese
patent: 4197578 (1980-04-01), Wada et al.
patent: 4876639 (1989-10-01), Mensch, Jr.
patent: 5117488 (1992-05-01), Noguchi et al.
patent: 5179691 (1993-01-01), O'Brien et al.
patent: 5335331 (1994-08-01), Murao et al.
patent: 5421029 (1995-05-01), Yoshida
patent: 5568646 (1996-10-01), Jaggar
patent: 5652852 (1997-07-01), Yokota
patent: 5740461 (1998-04-01), Jaggar
patent: 5758115 (1998-05-01), Nevill
patent: 5784585 (1998-07-01), Denman
patent: 5790824 (1998-08-01), Asghar et al.
patent: 5826089 (1998-10-01), Ireton
patent: 5828859 (1998-10-01), Tanihira et al.
patent: 5867681 (1999-02-01), Worrell et al.

Affiliated with

Also associated with

Rating

Processor instruction control mechanism capable of decoding regi does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Processor instruction control mechanism capable of decoding regi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Processor instruction control mechanism capable of decoding regi will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-311053