Processor including fallback branch prediction mechanism for...

Details Processor including fallback branch prediction mechanism for... Processor including fallback branch prediction mechanism for...

2006-10-03

2006-10-03

Kim, Kenneth S. (Department: 2111)

Electrical computers and digital processing systems: processing

Processing control

Branching

C711S209000, C711S220000, C712S238000, C712S240000

Reexamination Certificate

active

07117347

ABSTRACT:
A method and apparatus are provided for processing far jump-call branch instructions within a processor in a manner which reduces the number of stalls of the processor pipeline. The processor includes an apparatus, for providing a fallback far jump-call speculative target address that corresponds to a current far jump-call branch instruction. The microprocessor apparatus includes a far jump-call branch target buffer and a fallback speculative target address generator. The far jump-call branch target buffer stores a plurality of code segment bases and offsets corresponding to a plurality of previously executed far jump-call branch instructions, and determines if a hit for the current far jump-call branch instruction is contained therein. The fallback speculative target address generator is coupled to the far jump-call branch target buffer. In the event of a miss in the far jump-call branch target buffer, the fall back speculative target address generator generates the fallback far jump-call speculative target address from a current code segment base and a target offset, the target offset corresponding to the current far jump-call branch instruction.

REFERENCES:
patent: 5608886 (1997-03-01), Blomgren et al.
patent: 5740415 (1998-04-01), Hara
patent: 5740416 (1998-04-01), McMahan
patent: 5740418 (1998-04-01), Hara
patent: 5996071 (1999-11-01), White et al.
patent: 6108773 (2000-08-01), Col et al.
patent: 6609194 (2003-08-01), Henry et al.
Intel Architecture Software Developer's Manual, vol. 2: Instruction Set Reference. Intel Corporation, 1999. pp. 3-2 and 3-3.
The PowerPC Architecture: A Specification for a New Family of RISC Processors. Morgan Kauffman Publishers, Inc., 1994. pp. 4, 12-15 and 22-23.

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