Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate plural instruction...
Reexamination Certificate
1999-02-08
2001-07-10
An, Meng-Al T. (Department: 2154)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate plural instruction...
C712S043000, C712S208000, C712S210000, C712S214000, C712S215000, C712S216000
Reexamination Certificate
active
06260133
ABSTRACT:
TECHNICAL FIELD
This invention relates to a processor, particularly, of a type having an operation instruction which uses operation units in different pipelines simultaneously in a superscalar manner.
BACKGROUND
Various techniques are known for speeding up microprocessors. Among these speeding-up techniques, there is a technique called pipelining. Pipelining is a technique which divides the operation of an instruction into a plurality of stages and sequentially executes divisional parts from a stage to another to perform the instruction.
For example, a single instruction may be divided into four stages, namely, a fetch stage, an instruction decode stage, an execution stage and a write-back stage, and these stages are executed in one clock cycle. For the execution, different stages are executed in an overlapping manner. That is, while the instruction fetch of a single instruction is completed and its instruction decode is executed, the instruction fetch of the next instruction can be executed at the same time. By progressively processing instructions from one stage to another, instructions can be finished every clock cycle.
There is another known technique called “superscalar” for speeding up microprocessors. Superscalar is a technique where hardware from plurality of pipelines executes a plurality of instructions in parallel. When two pipelines are used, it is called two-way. When four pipelines are used, it is called four-way.
Superscalar uses one operating unit for one instruction. Let a processor include a first integer unit and a floating unit in its first pipeline, and a second integer unit and a load store unit in its second pipeline, for example. Assume here that the instruction fetch unit sent the first pipeline an instruction to use the first integer unit and the second pipeline an instruction to use the second integer unit. Then, operation is automatically executed by using the first integer unit and the second integer unit.
The conventional processor, however, cannot use the floating point unit in the first pipeline and the load store unit in the second pipeline while it uses the first integer unit and the second integer unit. That is, the conventional processor does not use its operating units efficiently. Thus, there is a desire for efficient use of various operating units in a processor and realization of a control method therefor.
SUMMARY
It is therefore an object of the invention to provide a processor capable of efficiently using various operating units in different pipelines and to provide a specific control circuit required therefor.
According to the invention, there is provided a processor comprising:
a first pipeline having a first operating unit for executing a first operation;
a second pipeline having a second operating unit for executing the same operation as the first operation, and a third operating unit for executing an operation different from the first operation;
an instruction fetch unit which issues to the first pipeline a first operating instruction to be operated by using one of the operating units in the first pipeline and the second pipeline a second operating instruction to be operated by using the first operating unit in the first pipeline and one of the operating units in the second pipeline, and issues the first operating instruction to the second pipeline; and
a control circuit activated when the instruction fetch unit issues to the first pipeline the second operating instruction to be operated by using the first operating unit and the second operating unit, and simultaneously issues to the second pipeline the first operating instruction to be operated by using the second operating unit to make control such that the first operating instruction be executed preferentially while holding the second operating instruction in wait if the first operating instruction is issued earlier than the second operating instruction, or the second operating instruction be executed preferentially while holding the first operating instruction in wait if the second operating instruction is issued earlier than the first operating instruction.
There is further provided a processor comprising:
a first pipeline having a first operating unit for executing a first operation and a second operating unit for executing a second operation;
a second pipeline having a third operating unit for executing a third operation and a fourth operating unit for executing a fourth operation;
an instruction fetch unit which issues to one of the first pipeline and the second pipeline a first operating instruction to be operated by using one of the operating units in the first pipeline and the second pipeline and a second operating instruction to be operated by using one of the first operating units in the first pipeline and one of the operating units in the second pipeline, and issues the first operating instruction to the other of the first pipeline and the second pipeline; and
a control circuit activated when the first operating instruction issued from the instruction fetch unit to one of the first pipeline and the second pipeline and the second operating instruction issued from the instruction fetch unit to the other of the first pipeline and the second pipeline need a common operating unit to make control such that the first operating instruction be executed preferentially while holding the second operating instruction in wait if the first operating instruction is issued earlier than the second operating instruction, or the second operating instruction be executed preferentially while holding the first operating instruction in wait if the second operating instruction is issued earlier than the first operating instruction.
There is further provided a processor comprising:
a first pipeline having a first operating unit for executing a first operation;
a second pipeline having a second operating unit for executing the same operation as the first operation, and a third operating unit for executing an operation different from the first operation;
an instruction fetch unit which issues to the first pipeline a first operating instruction to be operated by using one of the operating units in the first pipeline and the second pipeline and a second operating instruction to be operated by using the first operating unit in the first pipeline and one of the operating units in the second pipeline, and issues the first operating instruction to the second pipeline; and
a control circuit activated when the instruction fetch unit issues to the first pipeline the second operating instruction to be operated by using the first operating unit and the second operating unit, and simultaneously issues to the second pipeline the first operating instruction to be operated by using the second operating unit to make control such that one of the first operating instruction and the second operating instruction is held in wait while preferentially executing the other.
REFERENCES:
patent: 5555384 (1996-09-01), Roberts et al.
patent: 5598546 (1997-01-01), Blomgren
patent: 5627982 (1997-05-01), Hirata et al.
patent: 5867682 (1999-02-01), Witt et al.
patent: 5913049 (1999-06-01), Shiell et al.
patent: 6076159 (2000-06-01), Fleck et al.
patent: 6105127 (2000-08-01), Kimura et al.
U.S. application No. 09/244,443, Agarwal et al., filed Feb. 4, 1999.
An Meng-Al T.
Gray Cary Ware & Freidenrich LLP
Kabushiki Kaisha Toshiba
Lin Wen-Tai
LandOfFree
Processor having operating instruction which uses operation... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Processor having operating instruction which uses operation..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Processor having operating instruction which uses operation... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2457065