Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
Reexamination Certificate
2000-09-22
2004-08-31
Tsai, Henry W. H. (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Reducing an impact of a stall or pipeline bubble
C712S244000
Reexamination Certificate
active
06785803
ABSTRACT:
FIELD
The invention generally relates to processors, and in particular to the use of a replay queue to break livelocks or a stalled condition.
BACKGROUND
The primary function of most computer processors is to execute a stream of computer instructions that are retrieved from a storage device. Many processors are designed to fetch an instruction and execute that instruction before fetching the next instruction. However, in other processors, instructions can be executed out of order. In some out of order processors, there is a possibility that a livelock or a stalled condition can occur where the processor continues executing instructions, but the processor does not make forward progress (i.e., no additional instructions are retired). The livelock or stalled condition can occur for a number of different reasons. One example where a livelock can occur is in a multi-threaded processor where an instruction of one thread inhibits or precludes execution of the other threads. Current architectures do not adequately address the problem of livelocks.
Therefore, a need exists for a technique to detect and break livelocks in processors, including multi-threaded processors.
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Allen James D.
Merchant Amit A.
Sager David J.
Kacvinsky John F.
Tsai Henry W. H.
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