Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
1999-03-31
2001-11-27
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S009000, C712S005000, C712S007000, C712S011000, C712S016000
Reexamination Certificate
active
06324638
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to data processing and, in particular, to a processor and method for processing vector instructions. Still more particularly, the present invention relates to a processor and data processing method in which vector instructions operating on vector elements of differing lengths are executed with significant hardware reuse.
2. Description of the Related Art
Traditionally, many computer systems capable of performing numerically-intensive applications followed one of two architectures. According to a first architecture, a computer system includes a central processing unit (CPU) for performing system-control functions and one or more numerical processing circuits, for example, Digital Signal Processor (DSPs), math co-processors, Application Specific Integrated Circuits (ASICs) or the like, for performing specialized computations. Because of the use of both a general-purpose CPU and specialized numerical processing circuitry, this architecture can be useful in a broad range of applications in addition to just numerically-intensive applications. However, the inclusion of both specialized computational circuitry and a general-purpose CPU within a computer system introduces significant complexity in that multiple diverse instruction and data streams must be concurrently supported, as well as significant communication between the specialized computational circuitry and the general-purpose CPU.
According to a second architecture, a computer system is implemented as a vector processor having tens or hundreds of identical Arithmetic Logic Units (ALUs) for processing multiple variable-length vectors in parallel. That is, each ALU processes a different one-dimensional vector in a pipelined fashion, and all ALUs operate concurrently. This second architecture, while specifically tailored to scientific computing and thus avoiding some of the complexity of the first architecture, is not optimal for performing a broad range of non-numerically intensive applications.
In addition to these architectures, a third architecture, exemplified by the PowerPC™ Reduced Instruction Set Computing (RISC) architecture, has emerged. According to the PowerPC™ RISC architecture, a single-chip general-purpose microprocessor is equipped with multiple execution units, including separate execution units for performing integer and floating point operations, that execute in parallel on a single instruction stream. This superscalar architecture has the advantage of being able to efficiently execute numerically-intensive applications, which typically contain a large percentage of floating point operations, as well as other types of applications, which tend to contain fewer floating-point operations than integer operations. The PowerPC™ RISC architecture is described in numerous publications, including
PowerPC Microprocessor Family: The Programming Environments,
Rev 1 (MPCFPE/AD) and
PowerPC
604
™ RISC Microprocessor User's Manual
(MPC604UM/AD), which are incorporated herein by reference.
In accordance with the present invention, the computational capabilities of the PowerPC™ architecture have been expanded by the inclusion of an additional vector execution unit that operates concurrently with the other execution units on a single instruction stream. In contrast to the vector processing architecture described above, the vector execution unit within the PowerPC™ architecture can concurrently process all elements of one-dimensional fixed-length vector operands in parallel rather than one element at a time. The addition of vector processing capability to the general-purpose PowerPC™ architecture further accelerates its performance when executing numerically-intensive software applications.
SUMMARY OF THE INVENTION
In accordance with the present invention, a processor capable of executing vector instructions includes at least an instruction sequencing unit and a vector processing unit that receives vector instructions to be executed from the instruction sequencing unit. The vector processing unit includes a plurality of multiply structures, each containing only a single multiply array, that each correspond to at least one element of a vector input operand. Utilizing the single multiply array, each of the plurality of multiply structures is capable of performing a multiplication operation on one element of a vector input operand and is also capable of performing a multiplication operation on multiple elements of a vector input operand concurrently. In an embodiment in which the maximum length of an element of a vector input operand is N bits, each of the plurality of multiply arrays can handle both N by N bit integer multiplication and M by M bit integer multiplication, where N is a non-unitary integer multiple of M.
At least one of the multiply structures also preferably includes an accumulating adder that receives as a first input a result produced by that multiply structure and receives as a second input a result produced by another multiply structure. From these inputs, the accumulating adder produces as an output an accumulated sum of the results in response to execution of the same instruction that caused the multiply structures to produce the intermediate results. Thus, the processor supports vector multiplication and result accumulation in response to execution of a single vector instruction.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 4809275 (1989-02-01), Inoue et al.
patent: 4881168 (1989-11-01), Inagami et al.
patent: 5778241 (1998-07-01), Bindloss et al.
Elmer Thomas
Putrino Michael
Bracewell & Patterson L.L.P.
Carwell Robert M.
International Business Machines - Corporation
Pan Daniel H.
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