Inhibiting of a co-issuing instruction in a processor having...
Initializing function block registers using value supplying...
Injection control mechanism for external events
Input pipeline registers for a node in an adaptive computing...
Input replicator for interrupts in a simultaneous and...
Input/output support for processing in a mesh connected...
Input/output system with mask register bit control of memory...
Inserting decoder reconfiguration instruction for routine...
Instruction address generation and tracking in a pipelined...
Instruction alignment unit employing dual instruction queues for
Instruction alignment unit employing dual instruction queues for
Instruction alignment unit for routing variable byte-length...
Instruction branch mispredict streaming
Instruction buffer and method of controlling the instruction...
Instruction buffer for issuing instruction sets to an...
Instruction cache alignment mechanism for branch targets...
Instruction cache association crossbar switch
Instruction cache associative crossbar switch
Instruction cache configured to provide instructions to a microp
Instruction cache prefetch based on trace cache eviction