Instruction cache configured to provide instructions to a microp

Details Instruction cache configured to provide instructions to a microp Instruction cache configured to provide instructions to a microp

1998-04-23

2000-12-26

Pan, Daniel H.

Electrical computers and digital processing systems: processing

Processing control

Branching

712233, 712235, 712236, 712237, 712238, G06F 1500

Patent

active

061675105

ABSTRACT:
An apparatus including a banked instruction cache and a branch prediction unit is provided. The banked instruction cache allows multiple instruction fetch addresses (comprising consecutive instruction blocks from the predicted instruction stream being executed by the microprocessor) to be fetched concurrently. The instruction cache provides an instruction block corresponding to one of the multiple fetch addresses to the instruction processing pipeline of the microprocessor during each consecutive clock cycle, while additional instruction fetch addresses from the predicted instruction stream are fetched. Preferably, the instruction cache includes at least a number of banks equal to the number of clock cycles consumed by an instruction cache access. In this manner, instructions may be provided during each consecutive clock cycle even though instruction cache access time is greater than the clock cycle time of the microprocessor.

REFERENCES:
patent: 4044338 (1977-08-01), Wolf
patent: 4453212 (1984-06-01), Gaither et al.
patent: 4661900 (1987-04-01), Chen et al.
patent: 4807115 (1989-02-01), Torng
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 4928223 (1990-05-01), Dao et al.
patent: 5053631 (1991-10-01), Perlman et al.
patent: 5058048 (1991-10-01), Gupta et al.
patent: 5129067 (1992-07-01), Johnson
patent: 5136697 (1992-08-01), Johnson
patent: 5226126 (1993-07-01), McFarland et al.
patent: 5226130 (1993-07-01), Favor et al.
patent: 5392443 (1995-02-01), Sakakibara et al.
patent: 5526507 (1996-06-01), Hill
patent: 5557782 (1996-09-01), Witkowski et al.
patent: 5619602 (1997-04-01), Sandstrom et al.
patent: 5619662 (1997-04-01), Steely, Jr. et al.
patent: 5732243 (1998-03-01), McMahan
patent: 5748978 (1998-05-01), Narayan et al.
patent: 5752259 (1998-05-01), Tran
patent: 5761713 (1998-06-01), Lesartre
patent: 5809294 (1998-09-01), Ando
patent: 5812838 (1998-09-01), Dhong et al.
patent: 5828874 (1998-10-01), Steely, Jr. et al.
patent: 5835745 (1998-11-01), Sager et al.
patent: 5838943 (1998-11-01), Ramagopal et al.
Michael Slater, "AMD's K5 Designed to Outrun Pentium," Microprocessor Report, vol. 8, No. 14, Oct. 24, 1994, 7 pages.
Sebastian Rupley and John Clyman, "P6: The Next Step?," PC Magazine, Sep. 12, 1995, 16 pages.
Tom R. Halfhill, "AMD K6 takes On Intel P6," BYTE, Jan. 1996, 4 pages.
Patterson et al., Computer Architecture A Quantitative Approach, Morgan Kaufmann Publishers, Inc., 1990, pp. 361-363.
Intel, "Chapter 2: Microprocessor Architecture Overview," pp. 2-1 through 2-4.

Affiliated with

Also associated with

Rating

Instruction cache configured to provide instructions to a microp does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Instruction cache configured to provide instructions to a microp, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Instruction cache configured to provide instructions to a microp will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1006694