Instruction buffer for issuing instruction sets to an...

Details Instruction buffer for issuing instruction sets to an... Instruction buffer for issuing instruction sets to an...

1997-08-15

2001-06-12

Chan, Eddie (Department: 2783)

Electrical computers and digital processing systems: processing

Processing control

Branching

C712S206000, C712S215000

Reexamination Certificate

active

06247120

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to mechanisms for sequentially transferring instruction sets from an instruction buffer to an instruction decoder.
BACKGROUND OF THE INVENTION
The operation of an instruction buffer is to transfer instructions from a computer memory to an instruction decoder. As is known in the prior art, a computer memory may store a block of instructions. Segments of the block of instructions are transferred to a cache memory, as needed, and the cache memory in turn sequentially transfers the instructions to the instruction buffer.
The instruction buffer buffers the instructions from the cache memory to the instruction decoder. In this way, the cache memory is allowed operational versatility in that it does not have to perform hand-shaking operations with the instruction decoder. For example, the cache memory may be ready to send four instructions to the instruction decoder, but the instruction decoder may not be ready to receive the four instructions. The instruction buffer takes the instructions from the cache memory and holds the instructions for the instruction decoder until the instruction decoder is ready to receive the instructions.
FIG. 1
shows a conventional instruction buffer configuration wherein instructions are fed, one at a time, from a memory
101
to instruction buffer
103
(or, alternatively, directly to the four-to-one multiplexer
109
). With each cycle, instruction buffer
103
may receive one instruction from memory
101
, and address buffer
104
may receive the corresponding address. If instruction buffer
103
already has an instruction before it is to receive a second instruction from memory
101
, then that first instruction is fed to instruction buffer
105
(and the corresponding address in address buffer
104
is fed to address buffer
106
), before instruction buffer
103
and address buffer
104
receive the second instruction and address from memory
101
.
In the same way that the first instruction is shifted down from instruction buffer
103
upon receipt of a second instruction, a third instruction fed to instruction buffer
103
may cause the second instruction to shift to instruction buffer
105
and the first instruction to shift to instruction buffer
107
.
Instruction buffer
107
is connected at its output to the four-to-one multiplexer
109
, as are instruction buffers
103
and
105
at their respective outputs. Line
102
connects memory
101
directly to the four-to-one multiplexer
109
, such that instructions may by-pass the three instruction buffers
103
,
105
, and
107
altogether. When the three instruction buffers are not by-passed with line
102
, the four-to-one multiplexer
109
sequentially selects instructions from the three instruction buffers
103
,
105
, and
107
in the same order as they were fed from memory
101
. The four-to-one multiplexer
109
outputs instructions to instruction decoder
111
, one at a time.
The configuration of
FIG. 1
has several drawbacks. For instance, the system is only able to provide a single instruction to instruction decoder
111
for any given cycle. Also, the speed of the system is severely limited because of the bottleneck created at the memory
101
and instruction buffer
103
interface. That is, when the three instruction buffers are not by-passed, memory
101
can only feed instructions to the instruction buffer configuration as fast as instruction buffer
103
can accept the instructions which is at a speed of one instruction per cycle.
SUMMARY OF THE INVENTION
The present invention provides more versatility than the prior art in that it is able to accept from memory four instructions per cycle instead of just one, and is able to output instructions to an instruction decoder in combinations or one, two, three, or four instructions per cycle. The instruction buffer of the present invention includes a first storage area having four storage elements and a second storage area having three storage elements, for a total of seven storage elements. The first storage area initially inputs four instructions, and is configured to output one, two, three, or four instructions for any given cycle. The instruction buffer of the present invention is actually able to output up to seven instructions per cycle, but is optimized in the preferred embodiment to output up to four. In the case of seven, for example, four instructions would come from the first storage area and three instructions would come from the second storage area.
When a number of instructions (between one and four) are output from the first storage area, a number of vacancies equal to the number of instructions output is formed. The instruction buffer senses the number of instructions remaining, and shifts those remaining instructions in the first and second storage areas into the vacancies formed by the outputted instructions. The instruction buffer then determines, based on the sensed number, whether four additional instructions should be loaded into the second and first storage areas. This determination is based on whether the total number of instructions remaining, since the last loading of the second and first storage areas with four additional instructions, is less than or equal to three.
Upon a determination that the total number of instructions remaining since the last loading of the second and first storage areas is less than or equal to three, a determination is made that the second and first storage areas should be loaded with four additional instructions. Accordingly, four additional instructions are loaded into the second and first storage areas.


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Harry Dwyer III (A multiple, out-of-order, instruction issuing system for superscalar processors) pp. 1-23, Aug. 1991.

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