Electrical computers and digital processing systems: processing – Processing control – Processing control for data transfer
Reexamination Certificate
1999-11-29
2003-03-11
Ellis, Richard L. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Processing control for data transfer
C712S032000, C712S038000, C711S163000
Reexamination Certificate
active
06532533
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
Not Applicable
STATEMENT OF FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates in general to processing devices and, more particularly, to a general-purpose input/output subsystem.
2. Description of the Related Art
General-purpose processing devices, which may include microprocessing units (MPUs), digital signal processors (DSPs) and other devices, allow a single device to be used in many different applications. The processing device is customized to the desired application through programming. A single processing device may be used to execute multiple programs, separately or concurrently. The order in which applications are executed may change dynamically during operation of the processing device.
Many processing devices include general-purpose input/output (I/O) pins, which may be used by the programmers to interface the processing device to other devices. These I/O pins may be used as needed in a particular application. For example, a processing device used in a cellular phone may designate a first group of pins to connect to a modem circuit and a second group of pins to connect to an LCD screen controller. In another application these same pins could be for very different purposes.
In the prior art, the general-purpose I/O pins have been coupled to a I/O register that stores a value associated with each pin in a respective bit position of the register. To read pin signals for a certain function, the processor reads the value of the register and the processing device masks the bits not associated with the function. To send signals to pins for a certain function, the processor, to avoid changing bits not associated with the function, must perform a read-modify-write operation. The processor reads the value of the output buffer associated with the general-purpose I/O pins, modifies only those bits associated with the function at hand, and re-writes the modified value to the output buffer. This scheme of providing general-purpose I/O pins can use a significant amount of processing time and power, and requires tedious and scrupulous programming to operate the I/O pins correctly.
Another significant concern involves the use of the general-purpose I/O pins in a multi-tasking environment, where multiple independent tasks access the I/O register. In this case, the read-modify-write operation must be atomic, i.e., the entire operation must be completed before another operation begins. Otherwise, the following scenario could occur: (1) a first task performs a read-modify-write in order to write data to pins 0-3 of the general-purpose I/O pins, (2) second task interrupts the first task, after the read but before the write, and performs a read-modify-write to pins 4-6 of the general-purpose I/O pins, and (3) after completion of the second task's read-modify-write, the first task regains control and finishes its read-modify-write. In this case, the data for driving pins 4-6 would be overwritten by the write operation of the first task's read-modify-write. In order to prevent this situation from occurring, it is necessary to disable all interrupts to the processing core during the read-modify-write; disabling interrupts to the processing core can create unnecessary latencies in the operation of the device.
Accordingly, a need has arisen for general input/output pins in a processing device which can be easily programmed and which do not hamper processor performance.
BRIEF SUMMARY OF THE INVENTION
In the present invention, a processing device includes a plurality of mask registers, with each mask register having a plurality of bits. A plurality of input/output pins correspond to respective bits of each mask register. One or more data registers are coupled to the input/output pins, each of the data registers have a plurality of bits corresponding to respective bits of each mask register. Logic circuitry accesses the data registers only at locations defined by a selected one of said mask registers.
The present invention provides significant advantages over the prior art. The mask registers and logic allow the processing core to read and write information to the data registers associated with the general purpose I/O pins with a simple read or write command, without becoming involved in performing a read-modify-write operation. Further, the invention eliminates the possibility of errors due to interrupts of a read-modify-write operation. Also, the programming for reading and writing data to the pins is significantly simplified over the prior art and is less prone to error.
REFERENCES:
patent: 5713006 (1998-01-01), Shigeeda
patent: 5901328 (1999-05-01), Ooe
patent: 5923894 (1999-07-01), Sollars
Bhandal Amarjit S.
Short Graham
Simpson Richard
Brady III W. James
Ellis Richard L.
Marshall, Jr. Robert D.
Meonske Tonia L.
Telecky , Jr. Frederick J.
LandOfFree
Input/output system with mask register bit control of memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Input/output system with mask register bit control of memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Input/output system with mask register bit control of memory... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3070555