Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
Reexamination Certificate
2000-08-31
2004-04-27
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction issuing
Simultaneous issuance of multiple instructions
C712S206000, C712S217000, C712S219000, C712S226000, C712S245000, C712S041000, C711S173000
Reexamination Certificate
active
06728866
ABSTRACT:
BACKGROUND
1. Field of the Present Invention
The present invention generally relates to the field of microprocessors and more particularly to a microprocessor incorporating a partitioned issue queue and a method of allocating instructions thereto.
2. History of Related Art
In the field of microprocessor architecture, an issue queue generally provides a facility for storing instructions pending execution in one or more execution units associated with the issue queue. An execution unit typically includes facilities for updating a register file in which the instruction's operands are stored pending execution and in which the operation's results are stored following execution. If multiple instances of an execution unit are incorporated into the microprocessor architecture, each execution unit may include its own register file. When an instruction is executed in a particular execution unit, the result is generally posted to the register files associated with each execution unit in the event that an instruction in one of the other execution units requires the result to perform a given operation.
Thus, after completion of an instruction, a register file local to the execution unit that performed the operation is updated and one or more other register files associated with other execution units are updated as well. Typically, the register file local to the execution unit that executed an instruction is physically closer than the register files of other execution units. The difference in distance between a local register file and a remote register file results in a timing asymmetry within the processor. In other words, the result of an executed instruction is updated in the local register file before it is updated in a remote register file because of the greater interconnect delay path between the execution unit and the remote file.
Traditionally, asymmetries in the layout of a microprocessor were of little concern because the processor cycles times were sufficient to allow for a worst case delay path. With processor cycle times decreasing below 1 nanosecond, however, the delay path asymmetry could result in a situation where the time (number of processor cycles) required to execute a given sequence of instructions is could be affected by asymmetrical layout considerations. If a pair of instructions include an instruction dependency, the dependent instruction must wait until the result of the first instruction is posted to the register file of the execution unit to which the dependent instruction has been issued. If the dependent instruction is issued to a different execution unit than the first instruction, the interconnect delay associated with the remote register file could negatively impact performance. It would therefore be highly desirable to implement a microprocessor that included an issue queue capable of selectively issuing instructions to its associated execution units to minimize overall execution time. In addition, it would be further desirable if the implemented solution did not significantly increase the cost or complexity of the microprocessor's design and were transparent to a user (programmer) of the microprocessor.
SUMMARY OF THE INVENTION
A microprocessor and method of processing instructions that addresses the timing assymetries between functional units. A sequence of instructions including a first instruction and a second instruction are received. Dependency logic determines if any dependencies between the first and second instructions. The dependency logic then selects between first and second issue queue partitions for storing the first and second instructions pending issue based upon the dependency determination, wherein the first issue queue partition issues instructions to a first execution unit and the second issue queue partition issues instructions to a second execution unit. The first and second issue queue partitions may be asymmetric with respect to a first register file in which instruction results are stored. The first and second instructions are then stored in the selected partitions. Selecting between the first and second issue queue partitions may include selecting a common issue queue partition for the first and second instructions if there is a dependency between the first and second instructions and selecting between the first and second issue queue partition may be based upon a fairness algorithm if the first and second instructions lack dependencies.
REFERENCES:
patent: 5175829 (1992-12-01), Stumpf et al.
patent: 5509130 (1996-04-01), Trauben et al.
patent: 5892699 (1999-04-01), Duncan et al.
patent: 5978838 (1999-11-01), Mohamed et al.
Kahle James Allan
Moore Charles Roberts
Emile Volel
International Business Machines - Corporation
Lally Joseph P.
Pan Daniel H.
Tyson Thomas E.
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