Electrical computers and digital processing systems: processing – Instruction issuing
Reexamination Certificate
2005-02-04
2010-02-16
Kim, Kenneth S. (Department: 2111)
Electrical computers and digital processing systems: processing
Instruction issuing
C712S219000, C718S103000
Reexamination Certificate
active
07664936
ABSTRACT:
An apparatus for scheduling dispatch of instructions among a plurality of threads being concurrently executed in a multithreading processor is provided. The apparatus includes an instruction decoder that generate register usage information for an instruction from each of the threads, a priority generator that generates a priority for each instruction based on the register usage information and state information of instructions currently executing in an execution pipeline, and selection logic that dispatches at least one instruction from at least one thread based on the priority of the instructions. The priority indicates the likelihood the instruction will execute in the execution pipeline without stalling. For example, an instruction may have a high priority if it has little or no register dependencies or its data is known to be available; or may have a low priority if it has strong register dependencies or is an uncacheable or synchronized storage space load instruction.
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Jensen Michael Gottlieb
Jones Darren M.
Kinter Ryan C.
Vishin Sanjay
Kim Kenneth S.
MIPS Technologies Inc.
Sterne Kessler Goldstein & Fox P.L.L.C.
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