Electrical computers and digital processing systems: processing – Instruction issuing
Reexamination Certificate
2006-06-16
2008-05-27
Kim, Kenneth S. (Department: 2111)
Electrical computers and digital processing systems: processing
Instruction issuing
C711S220000, C712S200000
Reexamination Certificate
active
07380105
ABSTRACT:
A method and apparatus for improving the operation of a computer processor by utilizing an asymmetric clustered processor architecture are disclosed. The asymmetric clustered processor apparatus includes a narrow cluster, a wide cluster, a steering logic utilizing a cluster predictor for providing a decoded instruction to either the narrow cluster or the wide cluster; address registers which are not part of the ISA, and a translation look-aside buffer for translating the virtual address of a load/store instruction in parallel with an execute stage. The method includes the steps of: predictably steering the instruction to either a W-bit Wide integer cluster or an N-bit Narrow integer cluster, managing the Address register file, and processing any instruction in the Wide integer cluster but processing only N-bit instructions in the Narrow integer cluster.
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patent: 5805486 (1998-09-01), Sharangpani
patent: 6260133 (2001-07-01), Teruyama
patent: 7171609 (2007-01-01), Wilson et al.
patent: 2004/0181652 (2004-09-01), Ahmed et al.
R. González et al., “A Content Aware Integer Register File Organization,” 31st ISCA, Jun. 2004.
R. González et al., “An Asymmetric Clustered Processor based on Value Content,” 2005 Intl. Conference on Supercomputing.
Cortes Mateo Valero
Cristal Kestelman Adrian
Gonzalez Garcia Ruben
Veidenbaum Alexander V.
Kim Kenneth S.
Shimokaji & Associates P.C.
The Regents of the University of California
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