Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
Reexamination Certificate
2000-10-06
2004-07-13
Treat, William M. (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction issuing
Simultaneous issuance of multiple instructions
C712S241000, C712S022000, C712S035000
Reexamination Certificate
active
06763450
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to a processor for digital signal processing, and more specifically, it pertains to a processor that is equipped with a function that repeatedly executes one instruction over a number of clock cycles.
BACKGROUND OF THE INVENTION
For this type of processor, for example, the SIMD (Single-Instruction-Multiple-Data) type parallel processor is known. In a SIMD type parallel processor, a large number (normally, at least 100 units or more) of processing elements are arranged in parallel so that the same instruction is executed in parallel. Each processing element comprises a one bit DSP (Digital-Signal-Processor), and executes a single one-bit arithmetic operation within one clock cycle. Therefore, for example, to shift a single set of eight-bit data, a one-bit data shift is repeatedly conducted eight times over eight clock cycles. Also, in the addition of two sets of eight-bit data which results in a nine-bit sum (the highest-order bits of the data produce a carry bit), a one-bit addition calculation is repeatedly executed nine times over nine clock cycles. Understandably, because a large number of arithmetic operations are conducted simultaneously on a large number of processing elements, overall, the realization of high processing performance is possible.
In the above-mentioned SIMD type parallel processors, in the instruction execution unit that executes a common instruction on each processing element, besides the instruction (SIMD instruction) for the processing element, preparations are also made for instructions related to jump, sub-routine call, and hardware interrupt. Also, non-SIMD instructions are executed by an instruction execution unit that is separate from the processing element.
In conventional SIMD type parallel processors, the execution sequence for the program follows an order such that each instruction is executed serially one at a time without respect to whether it is an SIMD instruction or a non-SIMD instruction. Therefore, during the execution of an SIMD instruction in the instruction execution unit of a processing element, when a non-SIMD instruction is retrieved from the program memory, said non-SIMD instruction is placed in a standby condition until the execution of said SIMD instruction is completed, and after the execution of said SIMD instruction is completed, said non-SIMD instruction is executed in the above-mentioned instruction execution unit. Also, during the execution of a non-SIMD instruction, a NOP (No-Operation) instruction that designates the non-execution of an instruction is applied to the processing element. However, the processing of all the processing elements each time a non-SIMD instruction is executed is essentially stopped or suspended, and the processing performance is limited.
The present invention was designed in consideration of these problems, and its purpose is to offer a processor that improves the processing efficiency of a system that repeatedly executes one instruction over a large number of clock cycles.
Another purpose of the present invention is to offer a processor that can reduce the memory capacity required for program memory.
SUMMARY OF THE INVENTION
In order to achieve the above-mentioned purposes, one aspect of the present invention has a first instruction execution unit that repetitively executes a first-type instruction on one or a plurality of microprocessors, a second instruction execution unit that independently executes a second-type instruction from the above-mentioned first instruction execution unit, a program memory that stores a program containing instructions of the first type and instructions of the second type, an instruction read means that sequentially reads out instructions of the first type and the second type from the above-mentioned program memory according to the execution sequence for the program, and an instruction execution control means that, when an instruction of the second type is read from the above-mentioned program memory during the execution of an instruction of the first type, executes the instruction of said second type in the above-mentioned second instruction execution unit in parallel with the execution of the instruction of said first type in the above-mentioned first instruction execution unit.
Another aspect of the present invention, in regard to an instruction of the second type that is read from the program memory in the middle of the repetitive execution of an instruction of the first type in the first instruction execution unit, since the second instruction execution unit executes the instruction of the second type in parallel with the processing operation of the first instruction execution unit, the operating efficiency for the first instruction execution unit, and by extension, the throughput for the entire system, is increased.
In a third aspect of the present invention, preferably, the above-mentioned first instruction execution unit has a processing unit that executes the process designated by the instruction code of a first-type instruction within one clock cycle in units of one bit, a microinstruction register that, in regard to the above-mentioned instructions of the first type that are read from the above-mentioned program memory, applies the instruction code of that instruction to the above-mentioned processing unit as a microinstruction, an address counter that, for each instruction of the above-mentioned first type that is read from the above-mentioned program memory, sequentially applies to the above-mentioned processing unit data addresses related to those instructions while incrementing or decrementing in each single clock cycle from the initial value to the prescribed end value, and a repeat counter that, in regard to each instruction of the above-mentioned first type that is read from the above-mentioned program memory, counts the number of times the process designated by the above-mentioned instruction code is repeatedly executed in the above-mentioned processing unit.
A fourth aspect of the present invention preferably has a first-in first-out type memory that stores the instructions of the first type that are read from the above-mentioned program memory in a first-in first-out format, and provides the instructions of the first type that have been read to the first instruction execution unit.
In this case, even if an instruction of the second type that is to be executed simultaneously with the execution sequence of the instruction of the first type is read, the invention can have a construction wherein the instruction is temporarily stored in the first-in first-out type memory, and is executed in the second instruction execution unit at the point in time at which it is read from the first-in first-out type memory.
In a fifth aspect of the present invention, in order to reduce the required capacity of the program memory, it can be made a construction wherein a portion or all of each instruction is encoded and stored in the above-mentioned program memory, and a decoder is provided that decodes the instructions read from the above-mentioned program.
REFERENCES:
patent: 5210836 (1993-05-01), Childers et al.
Akiyama Tsuyoshi
Miyaguchi Hiroshi
Onuma Hidetoshi
Brady III W. James
Kempler William B.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Treat William M.
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