Processor

Details Processor Processor

2011-05-31

2011-05-31

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Instruction issuing

Simultaneous issuance of multiple instructions

Reexamination Certificate

active

07953959

ABSTRACT:
A processor includes: an instruction buffer which holds a group of instructions that can be executed in parallel; an instruction decoding unit which decodes part or all of the group of instructions; and an instruction issuance control unit which detects whether or not a factor obstructing simultaneous execution of the group of instructions exists in the group of instructions and supplies the group of instructions to the instruction decoding unit by controlling the instruction buffer so that the instructions of the group of instructions are sequentially supplied when the factor exists and all the instructions of the group of instructions are simultaneously supplied when the factor does not exist.

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English language Abstract of JP 3-259340.
English language Abstract of JP 6-332701.
English language Abstract of JP 2001-134442.
English language Abstract of JP 8-305567.
English language Abstract of JP 2001-92656.
English language Abstract of JP 8-221273.
U.S. Appl. No. 11/850,761 to Hosoki et al., which was filed on Sep. 6, 2007.
English language translation of Paragraphs [0023]-[0032] and Figures 1-5, 7 of JP 6-332701, Dec. 2, 1994.
English language translation of Paragraph [008] of JP 8-328859, Dec. 13, 1996.

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