Electrical computers and digital processing systems: processing – Instruction issuing
Reexamination Certificate
2007-12-31
2011-12-27
Pan, Daniel (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction issuing
C712S215000
Reexamination Certificate
active
08086825
ABSTRACT:
One or more processor cores of a multiple-core processing device each can utilize a processing pipeline having a plurality of execution units (e.g., integer execution units or floating point units) that together share a pre-execution front-end having instruction fetch, decode and dispatch resources. Further, one or more of the processor cores each can implement dispatch resources configured to dispatch multiple instructions in parallel to multiple corresponding execution units via separate dispatch buses. The dispatch resources further can opportunistically decode and dispatch instruction operations from multiple threads in parallel so as to increase the dispatch bandwidth. Moreover, some or all of the stages of the processing pipelines of one or more of the processor cores can be configured to implement independent thread selection for the corresponding stage.
REFERENCES:
patent: 5051885 (1991-09-01), Yates et al.
patent: 5193158 (1993-03-01), Kinney et al.
patent: 6061710 (2000-05-01), Eickemeyer et al.
patent: 6289442 (2001-09-01), Asato
patent: 7209996 (2007-04-01), Kohn et al.
patent: 7313676 (2007-12-01), Brekelbaum et al.
patent: 2003/0023834 (2003-01-01), Kalafatis et al.
patent: 2003/0046517 (2003-03-01), Lauterbach
patent: 2004/0210742 (2004-10-01), Levitan et al.
patent: 2006/0101238 (2006-05-01), Bose et al.
patent: 2006/0265555 (2006-11-01), Davis et al.
patent: 2007/0226464 (2007-09-01), Chaudhry et al.
patent: 2008/0263325 (2008-10-01), Kudva et al.
patent: 2009/0172359 (2009-07-01), Shen et al.
patent: 2009/0172370 (2009-07-01), Butler
patent: 1555610 (2005-07-01), None
patent: 03058501 (2003-07-01), None
Written opinion of the international preliminary examining authority, for PCT/US2008/013302 dated Jan. 26, 2010, 5 pages.
International Search Report for PCT/US2008/013302 dated Jun. 2, 2009, 4 pages.
Omondi, A. R. et al., “Performance of a context cache for a multithreaded pipeline,” Journal of Systems Architecture, Elsevier Science Publishers BV., Amsterdam, NL, vol. 45, No. 4, Dec. 1, 1998, pp. 305-322.
U.S. Appl. No. 11/967,924, Office Action mailed Mar. 5, 2010, 18 pages.
Chidester, M. et al., “Multiple-path Execution for Chip Multiprocessors,” HCS Research Laboratory, University of Florida; Feb. 2003; pp. 1-45.
Heil, T. et al., “Selective Dual Path Execution,” Technical Report, Department of Electrical and Computer Engineering, University of Wisconsin-Madison; Nov. 8, 1996; pp. 1-29.
Wallace, S. et al., “Threaded Multiple Path Execution,” Department of Computer Science and Engineering, Univeristy of California, San Diego; Jun. 1998; pp. 1-12.
El-Moursy, A. et al., “Partitioning Multi-Threaded Processors with a Large Number Of Threads,” 2005, pp. 1-12.
Non-Final Office Action mailed May 17, 2010 for U.S. Appl. No. 11/967,869, 20 pages.
Final Office Action mailed Jan. 19, 2011 for U.S. Appl. No. 11/967,869, 25 pages.
Notice of Allowance mailed May 21, 2010 for U.S. Appl. No. 11/967,924 8 pages.
Evers Marius
Lie Sean
Shen Gene
Advanced Micro Devices , Inc.
Pan Daniel
LandOfFree
Processing pipeline having stage-specific thread selection... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Processing pipeline having stage-specific thread selection..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Processing pipeline having stage-specific thread selection... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4311404