Passing decoded instructions to both trace cache building...

Details Passing decoded instructions to both trace cache building... Passing decoded instructions to both trace cache building...

2005-09-27

2005-09-27

Kim, Kenneth S. (Department: 2111)

Electrical computers and digital processing systems: processing

Instruction issuing

C711S118000, C712S205000

Reexamination Certificate

active

06950924

ABSTRACT:
A system and method of managing processor instructions provides enhanced performance. The system and method provide for decoding a first instruction into a plurality of operations with a decoder. A first copy of the operations is passed from the decoder to a build engine associated with a trace cache. The system and method further provide for passing a second copy of the operation from the decoder directly to a back end allocation module such that the operations bypass the build engine and the allocation module is in a decoder reading state.

REFERENCES:
patent: 6018786 (2000-01-01), Krick et al.
patent: 6055630 (2000-04-01), D'Sa et al.
patent: 6240509 (2001-05-01), Akkary

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