Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
Patent
1996-11-18
1999-11-30
Follansbee, John A.
Electrical computers and digital processing systems: processing
Instruction issuing
Simultaneous issuance of multiple instructions
712219, 711203, G06F 938
Patent
active
059960620
ABSTRACT:
An address translation memory stores a plurality of virtual address tags. The virtual address tags typically designate a portion of the virtual address space corresponding to a page of data stored in an intermediate storage device. A portion of an input virtual address is used to address the translation memory, and the resulting output virtual address tag is compared to a relevant portion of the input virtual address. If they match, then the requested data resides in the intermediate storage device, and an instruction issuing unit allows the instructions to continue issuing to an instruction pipeline as scheduled. However, if the virtual address tag does not match the relevant portion of the input virtual address, then it is assumed that a page fault might occur, and the instruction issuing unit inhibits the issuance of further instructions to the instruction pipeline. A page table stored in the second storage memory is then accessed to determine whether in fact the page corresponding to the input virtual address is stored in the second storage device. If so, then the instruction issuing unit resumes issuing instructions to the instruction pipeline. If not, then the page corresponding to the input virtual address is retrieved from first storage device and communicated to the second storage device, and the instruction issuing unit resumes issuing instructions to the instruction pipeline.
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Follansbee John A.
Intergraph Corporation
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