Management of both renamed and architected registers in a supers

Details Management of both renamed and architected registers in a supers Management of both renamed and architected registers in a supers

1997-03-11

1999-11-30

Maung, Zarni

Electrical computers and digital processing systems: processing

Instruction issuing

Simultaneous issuance of multiple instructions

712216, 712200, G06F 938

Patent

active

059960639

ABSTRACT:
The invention relates to the area of register renaming and allocation in superscalar computer systems. When a multitude of instructions in the instruction stream reads from or writes to a certain logical register, said logical register will have to be represented by a multitude of physical registers.
Therefore, there have to exist several physical rename registers per logical register. The oldest one of said rename registers defines the architected state of the computer system, the in-order state.
The invention provides a method for administration of the various register instances. Both the registers representing the in-order state and the various rename instances are kept in one common circular buffer. There exist two pointers per logical register: The first one, the in-order pointer, points to the register that represents the in-order state, the second one, the rename pointer, points to the most recent rename instance.

REFERENCES:
patent: 5367650 (1994-11-01), Sharangpani et al.
patent: 5371684 (1994-12-01), Iadonato et al.
patent: 5560032 (1996-09-01), Nguyen et al.
patent: 5694564 (1997-12-01), Alsup et al.
patent: 5721855 (1998-02-01), Hinton et al.
patent: 5737624 (1998-04-01), Garg et al.
patent: 5765215 (1998-06-01), Afsar et al.

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