Electrical computers and digital processing systems: processing – Instruction issuing
Reexamination Certificate
2000-03-06
2003-07-15
Niebling, John F. (Department: 2812)
Electrical computers and digital processing systems: processing
Instruction issuing
C712S216000
Reexamination Certificate
active
06594753
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to the field of microprocessors which are capable of processing at least two program instructions at the same time.
Modern microprocessors, including superscalar microprocessors, have improved performance due to the capability of processing at least two program instructions at the same time. This capability arises from having a first group of execution units which can receive a program instruction for execution, and a second group of execution units which can receive a second program instruction for execution.
FIG. 1
shows a typical microprocessor of the prior art which uses a dual issue mechanism wherein two program instructions may be issued to two groups of execution units. The register file
30
and the issue control and bypass control unit
12
support the issuance of two instructions, one instruction going to the execution units
14
,
16
, and
18
(issue left) and another instruction going to the execution units
20
,
22
, and
24
(issue right). Within each group of execution units, there are three specialized functional units. In particular, the execution units on the issue left side include a floating point division execution unit
14
, a floating point multiplier execution unit
16
, and an ALU execution unit
18
. In the group of execution units on the issue right side, there is a floating point adder execution unit
20
, an ALU execution unit
22
, and an integer multiplier unit
24
. Each of these execution units is coupled to the issue control and bypass control unit
12
by a bi-directional link which provides instructions from the issue control unit
12
to the particular execution unit and which provides a signal indicating the execution unit is busy to the issue control and bypass control unit
12
. In this manner, the issue control and bypass control unit
12
can determine the status of each execution unit (e.g. is the particular execution unit busy executing an instruction previously provided?) and can provide instructions for execution if the particular execution unit is not busy. These links are shown as
31
A-
31
F in FIG.
1
. The issue control and bypass unit
12
is coupled to an instruction cache
10
through a bus
11
. It will be appreciated that the issue control unit
12
provides read commands to the instruction cache
10
to cause the instruction cache
10
to deliver one or two instructions at a time to the issue control unit
12
.
Each execution unit within a group of execution units is coupled to an output of a multiplexer in order to receive operands which are processed according to the instruction being executed in the particular execution unit. These operands are received from either the register file
30
or from a bypass pathway in which an output from a prior executed instruction is used as an operand for a current instruction. The multiplexer
26
receives an output
30
b
from the register file and also receives an output from each of the six execution units and provides a selected output to the three execution units
14
,
16
, and
18
in the issue left group of execution units. The multiplexer
28
receives an output
30
a
from the register file
30
and also receives outputs from each of the six execution units, and provides an output which is selected by the control select line
15
. This output is provided to the three execution units
20
,
22
, and
24
in the issue right execution group. The six outputs
32
a
,
32
b
,
32
c
,
32
d
,
32
e
, and
32
f
from the six execution units
14
,
16
,
18
,
20
,
22
, and
24
are provided to both multiplexers
26
and
28
and also provided to the register file
30
as inputs to the register file
30
. It will be appreciated that the register file
30
may be configured to provide dual port reads such that operand outputs
30
a
and
30
b
can be provided based upon the addresses provided over address bus
17
from the control unit
12
. Moreover, the register file
30
may support multiple writes, such as six multiple write ports from the six outputs. It will also be appreciated that in typical operation of the microprocessor shown in
FIG. 1
, only two of the write ports will be active at once since normally only one result of a computation is provided from the issue left side and only one execution result is provided from the issue right side.
The operation of the microprocessor shown in
FIG. 1
will now be described. The issue control unit
12
receives two instructions from the instruction cache
10
. The issue control unit
12
then decodes each instruction to determine the resources or functions to be performed as required by the particular instruction. For example, if an instruction requires floating point division or floating point multiplication, then this instruction must be steered into the issue left group of execution units. Similarly, if a decoded instruction reveals that a floating point addition or integer multiplication is required by the instruction, then it must be issued to the issue right group of execution units. Thus, decoding in the issue control and bypass control unit
12
is required in order to determine whether an instruction goes to issue left or to issue right.
The issue control and bypass control unit
12
must also perform the resolution of execution unit conflicts before issuing an instruction. The following table shows an example of the stall logic in the issue control unit
12
in order to resolve execution unit conflicts. If there is an execution unit conflict indicated by a “X”, then the issue control will stall the issue of the instruction.
TABLE A
Issue
Instruction
Instruction in Unit:
Type
FP Div
FP Mult
FP Add
ALU 0
ALU 1
Int Mult
FP Div
X
FP Mult
X
FP Add
X
ALU 1
X
X
Int Mult
X
For example, if the issue instruction is of the type “FP Div” (i.e., the instruction is for a floating point division), the instruction will stall if there is an instruction in the floating point division unit
14
which is currently being executed by the floating point execution unit
14
.
The issue control and bypass unit
12
also stalls the issuance of instructions in order to resolve register conflicts.
TABLE B
Issue
Instruction
Instruction in Unit:
Registers
FP Div
FP Mult
FP Add
ALU 0
ALU 1
Int Mult
Operand 1
X
X
X
X
X
X
Operand 2
X
X
X
X
X
X
Destination
X
X
X
X
X
X
If there is a register match between any of the registers indicated by “X”, then the issue control unit
12
will stall the issue on the instruction. For example, if for a particular instruction which is yet to be issued, if the first operand for the instruction is to be stored in the same register as the destination register for a floating point division operation which is currently being executed, then the yet to be issued instruction will be stalled.
The issue control unit
12
also resolves resource conflicts at the register file
30
which arise because different instructions have different processor cycle times. This is shown by way of example in Table C below.
TABLE C
Cycle
ALU0
ALU1
FP Mult
FP Add
1
—
—
Issue
—
2
—
—
Execute
Issue
3
—
—
Execute
Execute
4
Issue
Issue
Execute
Execute
5
Write Result
Write Result
Write Result
Write Result
As can be seen from Table C, in Cycle 5 there are four results that are produced. Unless there are four write ports into the register file which contains a plurality of registers, the issue of instructions for the ALU0 and ALU1 in Cycle 4 may need to be stalled.
As can be seen from the foregoing description, the issue control unit must perform a variety of control operations in order to resolve various conflicts and yet attempt to issue two program instructions substantially concurrently if possible. It will be appreciated that such control, such as the decoding of program instructions in order to steer the instruction into the appropriate group of execution units, requires considerable circuitry and also requires considerable time in designing such a control unit for this type of microprocessor.
In many circumstances, it will be desirable to provide a microprocessor which req
Choquette Jack
Yeung Norman K.
Blakely , Sokoloff, Taylor & Zafman LLP
SandCraft, Inc.
Whitmore Stacy A
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