Method and apparatus for dispatching instructions to execution u

Details Method and apparatus for dispatching instructions to execution u Method and apparatus for dispatching instructions to execution u

1998-04-30

2000-08-15

Eng, David Y.

Electrical computers and digital processing systems: processing

Instruction issuing

Simultaneous issuance of multiple instructions

G06F 1500

Patent

active

061051284

ABSTRACT:
A first embodiment provides an apparatus including a first execution unit capable of executing a first type and a second type of ready instruction, a second execution unit capable of executing the second type of ready instruction, and a scheduler. The scheduler dispatches the instructions in waves and dispatches the first type of ready instruction to the first execution unit with a higher priority than the second type of ready instruction. The scheduler is capable of dispatching a second type of ready instruction to the second execution unit. A second embodiment provides a method of dispatching instructions in a processor having a scheduler, a first execution unit, and a second execution unit is provided. The method includes dispatching a first type of ready instruction to the first execution unit with a higher priority than dispatching a second type of ready instruction to the first execution unit in each wave. The method includes dispatching the second type of instruction to the second execution unit, the two steps of dispatching being performed in a wave.

REFERENCES:
patent: 5815724 (1998-09-01), Mates
patent: 5913049 (1999-06-01), Shiell et al.

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