Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
Reexamination Certificate
1999-12-03
2002-02-26
Treat, William M. (Department: 2783)
Electrical computers and digital processing systems: processing
Instruction issuing
Simultaneous issuance of multiple instructions
C712S216000, C712S213000, C712S207000, C711S125000, C711S129000
Reexamination Certificate
active
06351802
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of computer processor architecture. In particular the present invention discloses a method and apparatus for scheduling computer instructions.
BACKGROUND OF THE INVENTION
Early computer processors executed computer instructions one at a time in the original program order. Specifically, each computer instruction is loaded into the processor and then executed. After execution, the results of the computer instruction are then written into a register or into main memory. After the execution of a computer instruction, the next sequential computer instruction is then loaded into the processor and executed.
To improve performance, pipelined computer processors were introduced. Pipelined computer processors process multiple computer instructions simultaneously. However, early pipelined computer processors execute the instructions in the original program order. Pipelined processors operate by dividing the processing of instructions into a series of pipeline stages such as instruction fetch, instruction decode, execution, and result write-back. The processor is then divided into a set of linked pipeline stages that each perform one of the instruction processing pipeline stages. In the previously described example, the processor would be divided into an instruction fetch stage, an instruction decode stage, an execution stage, and write-back stage. During each clock cycle, each processing stage processes an instruction and then passes it to the next sequential processing stage. Thus, the processor is processing several instructions simultaneously in the original program order. In an ideal single pipeline processor, the processor will complete the execution of an instruction during every clock cycle.
To further improve processor performance, superscalar processors have been introduced. Superscalar processors process more than one instruction at a time using parallel pipeline stages. By executing instructions in parallel, superscalar processors take advantage of the parallelism that exists in the instructions. Parallelism exists when sequential computer instructions are not dependent upon each other for source operands. These non dependent sequential instructions can be executed in parallel without any data conflicts.
One of the difficult aspects of designing superscalar processors is to find and schedule instructions in parallel such that there are no data dependency violations and sufficient processor resources are available.
SUMMARY OF THE INVENTION
According to one embodiment, a method of scheduling instructions in a computer processor is provided. The method comprises fetching instructions to create an in-order instruction buffer, and scheduling instructions from the in-order instruction buffer into instruction slots within instruction vectors in an instruction vector table. Instruction vectors are then dispatched from the instruction vector table to a prescheduled instruction cache, and, in parallel, to an instruction issue unit.
REFERENCES:
patent: 5127093 (1992-06-01), Moore, Jr.
patent: 5295249 (1994-03-01), Blaner et al.
patent: 5442760 (1995-08-01), Einar et al.
patent: 5669011 (1997-09-01), Alpert et al.
patent: 5742784 (1998-04-01), Potter et al.
patent: 5794003 (1998-08-01), Sachs
patent: 5913049 (1999-06-01), Shiell et al.
patent: 5923862 (1999-07-01), Nguyen et al.
patent: 5933850 (1999-08-01), Kumar et al.
patent: 6212623 (2001-04-01), Witt
patent: 6253313 (2001-06-01), Morrison et al.
patent: 0605927 (1994-07-01), None
patent: 1050808 (2000-11-01), None
Minagawa et al., “Pre-decoding Mechanism for Supersealar Architecture”, IEEE Pacific Rom, May 9-10, 1991.*
Conference on Communications, Computers, and Signal Processing, vol. 1, pp. 21-24.*
International Search report for PCT/NO90/00143, Dated Apr. 4, 1991.
International Search report for PCT/US96/08255, Dated Dec. 5, 1996.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Treat William M.
LandOfFree
Method and apparatus for constructing a pre-scheduled... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for constructing a pre-scheduled..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for constructing a pre-scheduled... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2958550