Method and apparatus for executing instructions

Details Method and apparatus for executing instructions Method and apparatus for executing instructions

2007-10-24

2011-12-20

Treat, William M (Department: 2181)

Electrical computers and digital processing systems: processing

Instruction issuing

Simultaneous issuance of multiple instructions

C712S216000

Reexamination Certificate

active

08082420

ABSTRACT:
A method and apparatus for executing instructions in a processor are provided. In one embodiment of the invention, the method includes receiving a plurality of instructions. The plurality of instructions includes first instructions in a first thread and second instructions in a second thread. The method further includes forming a common issue group including an instruction of a first instruction type and an instruction of a second instruction type. The method also includes issuing the common issue group to a first execution unit and a second execution unit. The instruction of the first instruction type is issued to the first execution unit and the instruction of the second instruction type is issued to the second execution unit.

REFERENCES:
patent: 2007/0214343 (2007-09-01), Lindholm et al.
Mauricio Serrano, Performance Tradeoffs in Multistreamed Superscalar Processors, Dissertation, Univ. of California at Santa Barbara, Mar. 1994.

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