Electrical computers and digital processing systems: processing – Instruction issuing
Reexamination Certificate
2005-10-11
2005-10-11
Kim, Kenneth S. (Department: 2111)
Electrical computers and digital processing systems: processing
Instruction issuing
C712S205000, C712S216000
Reexamination Certificate
active
06954848
ABSTRACT:
After an instruction loads data into a register at a first time, the register is monitored to see if it is read in a next clock cycle. When the data is not read in the next clock cycle, the instruction is classified as a slowable instruction. An instruction address associated with the instruction is used to update a history table. The history table stores information to indicate if an instruction is a slowable instruction or a non-slowable instruction. When the instruction address of the instruction is encountered at a second time, the history table is used to determine if the instruction is slowable or non-slowable.
REFERENCES:
patent: 5442761 (1995-08-01), Toda et al.
patent: 5815698 (1998-09-01), Holmann et al.
patent: 6553484 (2003-04-01), Sawamura
Black Bryan
Brekelbaum Edward
Grochowski Edward
Rakvic Ryan
Shen John
Intel Corporation
Kim Kenneth S.
Tran David N.
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