Making available instructions in double slot FIFO queue...

Details Making available instructions in double slot FIFO queue... Making available instructions in double slot FIFO queue...

2000-05-02

2004-04-20

Kim, Kenneth S. (Department: 2181)

Electrical computers and digital processing systems: processing

Instruction issuing

C712S024000, C712S213000, C712S215000

Reexamination Certificate

active

06725357

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a system and in particular but not exclusively to a system for use in a computer system.
BACKGROUND OF THE INVENTION
Reference will now be made to
FIG. 5
which shows an arrangement considered by the present applicant. This Figure shows three execution units EXE A, EXE B and EXE C which are arranged to receive instructions from a first-in-first-out buffer of which one array
400
is shown. Each array
400
has two slots A and B. The first slot A can have instructions for the first execution unit EXE A or the third execution unit EXE C. The second slot B can have instructions for the second execution unit EXE B or the third execution unit EXE C. The output of the first slot A is input to the first execution unit EXE A and to a multiplexer
402
. Likewise the output of the second slot B is input to the second execution unit EXE B and to the multiplexer
402
. The output of the multiplexer
402
is input to the third execution unit EXE C.
When the first and second slots A and B contain instructions for the first and second execution unit EXE A and B, the instructions are output to these execution units at the beginning of a clock cycle. The execution units thus have and are able to act on these instructions at the beginning of that clock cycle. If, however, the instructions are intended for the third execution unit EXE C the instructions are output at the beginning of the multiplexer
402
and then to the third execution unit EXE C. This means that the instructions will not be available to the third execution unit EXE C at the beginning of the clock cycle. This can cause timing problems.
Reference is made to
FIG. 6
which shows the timing for the circuit of FIG.
5
.
FIG. 6
a
shows the clock signal.
FIG. 6
b
shows the timing of data for the first and second execution units EXE A and EXE B.
FIG. 6
c
shows the timing of data for the third execution unit EXE C. As can be seen from
FIG. 6
b
, time
0
represents the time taken for data to arrive at the first and second execution unit EXE A,B.
FIG. 6
c
shows the delay introduced by the multiplexer
402
. This time represents the time taken for data to arrive at the third execution unit.
As shown in
FIG. 6
time is wasted in driving the multiplexer
402
to send data to the third execution unit EXE C. As a result not as many operations can be performed on data in the third execution unit EXE C as compared to the first and second execution units EXE A and B.
SUMMARY OF THE INVENTION
It therefore an aim of embodiments of the present invention to address these problems.
According to one aspect of the present invention, there is provided a system comprising: a first execution unit, a second execution unit and a third execution unit; a first-in-first-out memory arranged to receive a plurality of instructions for said first to third execution units and to output said instructions to the execution units; a memory store for storing at least one instruction for one of said execution units, said at least one instruction being received from said first-in-first-out memory, said first and second execution units being arranged to receive their instructions from said first-in-first-out memory and said third execution unit being arranged to receive said instructions from said memory store, wherein a given instruction for said third execution unit is available to the third execution unit at substantially the same time that the instruction would be available to the first or second execution unit if that instruction was for said first or second execution unit.
In this way the timing problems of the arrangement shown in
FIG. 5
can be avoided.
Preferably, said first-in-first-out memory comprises a plurality of memory arrays, said memory array for storing instructions. Each array may comprise a first slot and a second slot each of which is able to store separate instructions. A first of said slots may contain instructions for said first execution unit and the second of said slots may contain instructions for said second execution unit. The third execution unit may be arranged to receive instructions from both of said slots. An instruction for said third execution unit may comprise instructions in said first and second slots.
Preferably, at least one of said first and second slots contains information identifying the execution unit for which the instruction is intended. In preferred embodiments of the invention, both of the slots contain information identifying the execution unit for which the instruction is intended.
Switch means may be provided between a first of said arrays and a second of said arrays for directing instructions to said first array and said memory store. The switch means may comprise at least one multiplexer. Preferably two multiplexers are provided, said first multiplexer being connected to the first slot of the first array and the second multiplexer being connected to the second slot of said array. The output of said first and second multiplexers may be output to said memory store.
Preferably, the output of said switch means is arranged to be input to a further switch means the output of which is connected to said memory store, said further switch means being arranged to pass only instructions intended for said third execution unit to said memory store. The further switch means may comprise a multiplexer. The memory store may be arranged to store only a single instruction. The memory store may be a flip flop.
The execution units are arranged to carry out pipelined operations in accordance with the instructions. Preferably, said first and second execution units are of one type and said third execution unit is of a second, different type. Instructions for said first to third execution units may be available at the beginning of a clock cycle.
According to a second aspect of the present invention there is provided an integrated circuit incorporating the above system.


REFERENCES:
patent: 5115496 (1992-05-01), Nomura
patent: 5241644 (1993-08-01), Nomura et al.
patent: 5560028 (1996-09-01), Sachs et al.
patent: 5617549 (1997-04-01), DeLano
patent: 5974537 (1999-10-01), Mehra
patent: 6304953 (2001-10-01), Henstrom et al.
patent: 0 667 571 (1995-08-01), None
patent: 0 690 373 (1996-01-01), None

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