Word selection logic to implement an 80 or 96-bit cache SRAM

Word selection logic to implement an 80 or 96-bit cache SRAM

Worm magnetic storage device

Write back and invalidate mechanism for multiple cache lines

Write back cache memory control within data processing system

Write barrier for data storage integrity

Write cache for servicing write requests within a predetermined

Write combining buffer that supports snoop request

Write latency efficient storage system

Write once read only registers

Write posting memory interface with block-based read-ahead...

Write-back cache having sub-line size coherency granularity and

Write-back disk cache

Write-combining device for uncacheable stores

Write-invalidate cache system for a split transaction bus based

Writeback cache cell with a dual ported dirty bit cell and metho

Writing cached data to system management memory

Zero delay data cache effective address generation