Write-combining device for uncacheable stores

Details Write-combining device for uncacheable stores Write-combining device for uncacheable stores

1999-04-15

2001-12-25

Elmore, Reba I. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S119000, C711S123000

Reexamination Certificate

active

06334171

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the transfer of data to memory in a computer system, and in particular relates to the write-combining of uncacheable data.
BACKGROUND INFORMATION
In a computer system, a piece of data which is to be transferred from a processor to some form of memory may be referred to as a “store.” A “store” (as the term is used herein) may generally include a piece of data or a block of data, address information, and an instruction to transfer the data in memory. In many situations stores are transferred, or “committed,” to various caches, which may be included within the processor or otherwise associated with the processor. Certain stores, however, are not amenable to cache storage. Instead, these “uncacheable stores” (“UC stores”) must be committed to system memory, such as dynamic random access memory (“DRAM”), other similar memory, or, if suitable, a more permanent storage medium such as a hard drive.
In known processors and systems, UC stores are committed in the form received. That is, stores are committed to memory in the form originally sent, or “executed,” by the processor (i.e., in “programatic” order). Because of varying sizes of these stores, however, direct commission to system memory fails to take advantage of the full bandwidth of the bus between the processor and memory. As a result, backups may occur between the processor and memory.
Based on the foregoing, there is a need for a device which makes more efficient use of the bandwidth between the processor and memory, thereby minimizing backups and hardware requirements.
SUMMARY OF THE INVENTION
A write-combining device for write-combining uncacheable stores is provided, including a memory order buffer and a data cache address and control. The memory order buffer receives a first store and a second stores. The data cache address and control is coupled to the memory order buffer and has at least one storage buffer. The data address and control receives the first and second stores from the memory order buffer, the first and second stores being write-combined in the storage buffer if the first and second stores are uncacheable and contiguous in memory.


REFERENCES:
patent: 5561780 (1996-10-01), Glew et al.
patent: 5630075 (1997-05-01), Joshi et al.
patent: 6122715 (2000-09-01), Palanca et al.

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