Write-back cache having sub-line size coherency granularity and

Details Write-back cache having sub-line size coherency granularity and Write-back cache having sub-line size coherency granularity and

1996-03-15

1998-09-01

Gossage, Glenn

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711144, 711141, 711128, G06F 1300, G06F 1200

Patent

active

058025723

ABSTRACT:
A write-back cache memory and method for maintaining coherency within a write-back cache memory are disclosed. The write-back cache memory includes a number of cache lines for storing data associated with addresses within an associated memory. Each of the cache lines comprises multiple byte sets. The write-back cache memory also includes coherency indicia for identifying each byte set among the multiple byte sets within a cache line which contains data that differs from data stored in corresponding addresses within the associated memory. The write-back cache memory further includes cache control logic, which, upon replacement of a particular cache line within the write-back cache memory, writes only identified byte sets to the associated memory, such that memory accesses and bus utilization are minimized.

REFERENCES:
patent: 4811209 (1989-03-01), Rubinstein
patent: 4914573 (1990-04-01), Scales, III et al.
patent: 5014195 (1991-05-01), Farrell et al.
patent: 5029070 (1991-07-01), McCarthy et al.
patent: 5155824 (1992-10-01), Edenfield
patent: 5301296 (1994-04-01), Mohri et al.
patent: 5586297 (1996-12-01), Bryg et al.

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