Writeback cache cell with a dual ported dirty bit cell and metho

Details Writeback cache cell with a dual ported dirty bit cell and metho Writeback cache cell with a dual ported dirty bit cell and metho

1997-09-05

2000-04-25

Lane, Jack A.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711143, 711156, 36523005, G06F 1200

Patent

active

060556064

ABSTRACT:
A writeback cache cell and method for operating a writeback cache. In one example, the method includes reading a memory cell of the writeback cache through a first port to determine whether the memory cell stores a first value which indicates that a memory location in the writeback cache has updated data relative to data stored in another memory and writing the first value to the memory cell through a second port if the reading step determined that the memory cell did not store the first value. An example of a writeback cache cell includes a memory cell storing a first value which indicates that a memory location in the writeback cache has updated data relative to data stored in another memory location when the data stored in the another memory location is invalid and includes a first port coupled to the memory cell and a second port coupled to the memory cell. The first port is used to read the memory cell to determine if the memory cell is storing the first value, and the second port is used to write the first value to the memory cell.

REFERENCES:
patent: 5781924 (1998-07-01), Zaitzeva et al.
patent: 5860158 (1999-01-01), Pai et al.
patent: 5900016 (1999-05-01), Ghosh

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