Write back and invalidate mechanism for multiple cache lines

Details Write back and invalidate mechanism for multiple cache lines Write back and invalidate mechanism for multiple cache lines

2006-02-14

2006-02-14

McLean-Mayo, Kimberly (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S140000, C711S135000, C711S137000, C712S226000, C712S207000

Reexamination Certificate

active

07000081

ABSTRACT:
A microprocessor apparatus is provided that enables write back and invalidation of a block of cache lines from memory. The apparatus includes translation logic and execution logic. The translation logic translates a block write back and invalidate instruction into a micro instruction sequence that directs a microprocessor to write back and invalidate a block of cache lines from cache to memory, where the number of cache lines in the block has been previously entered in a register in the microprocessor by a preceding micro instruction. The execution logic is coupled to the translation logic. The execution logic receives the micro instruction sequence, and issues transactions over a memory bus that writes back data corresponding to each of the cache lines within the block.

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