Write-invalidate cache system for a split transaction bus based

Details Write-invalidate cache system for a split transaction bus based Write-invalidate cache system for a split transaction bus based

1996-12-18

1998-06-02

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711121, 711145, G06F 1202

Patent

active

057617244

ABSTRACT:
A shared memory multiprocessor comprises a system bus operating under a split transaction protocol, at least one memory module coupled to the system bus and plurality of processor modules respectively having a processor and a cache. The cache maintains state information for each data block stored therein, which includes two distinct invalidated cache block states of COPYBACK-INVALID and NON-COPYBACK-INVALID. COPYBACK-INVALID and NON-COPYBACK-INVALID states commonly denote that the data block has been invalidated by another processor module in the shared memory multiprocessor. However, unlike COPYBACK-INVALID state, NON-COPYBACK-INVALID state further denotes that the processor module which most recently invalidated the data block has not copied back its updated copy of the block to the memory module, and, accordingly, the memory module does not contain the updated copy of the data block. Hence, upon an invalidation miss for a data block in a processor module, when the data block is in NON-COPYBACK-INVALID state as indicated by the state information of the data block, the processor module sends a read (with invalidation) request to other processor modules only, excluding the memory module from the read (with invalidation) request transaction.

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