Write cache for servicing write requests within a predetermined

Details Write cache for servicing write requests within a predetermined Write cache for servicing write requests within a predetermined

1995-06-05

1998-06-02

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711143, 711144, G06F 1208

Patent

active

057617090

ABSTRACT:
A memory system has a level 1 cache and a write cache connected to a processor, wherein the write cache has a memory address range and wherein the processor initiates a write to the write cache which is detected by the write cache. The write cache responds to the write request by storing information into the write cache if the write cache is not already full. If there is no storage location available in the write cache, a message is sent to the level 1 cache notifying that cache of this condition. The write cache responds to requests from the processor to write information stored in particular areas of the write cache into a main memory by placing that information on a external bus to be read by the main memory. The write cache then frees up those storage locations within the write cache to be used for storing subsequent writes requested by the processor.

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Chen, Yung-Chin and Veidenbaum, Alexander V. "An Effective Write Policy for Software Coherence Schemes", IEEE Computer Society Press, 1992; pp. 661-72.
Anon., "Dynamic Memory Architecture Increases Performance of 486-Based Motherboards", Electronic Design, vol. 41, No. 15, Jul. 1993, pp. 36-38.

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