Word selection logic to implement an 80 or 96-bit cache SRAM

Details Word selection logic to implement an 80 or 96-bit cache SRAM Word selection logic to implement an 80 or 96-bit cache SRAM

1996-06-13

1999-09-28

Bragdon, Reginald G.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395307, 395312, 395309, G06F 1316, G06F 1340, G06F 1208

Patent

active

059604530

ABSTRACT:
A logic which enables implementation of a 80-bit wide or a 96-bit wide cache SRAM using the same memory array. The logic implementation is accomplished by merging tag, and data into an order block of information to maximize bus utilization. The logic reduces the bus cycles from four cycles for an 80-bit to three cycles for a 96-bit implementation.

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