Modulo addressing

Modulo arithmetic

Modulus address generator and method for determining a...

Multi-hit control method for shared TLB in a multiprocessor...

Multi-level page cache for enhanced file system performance...

Multi-mode memory addressing using variable-length

Multi-processor system which provides for translation look-aside

Multi-sequence burst accessing for SDRAM

Multi-set block erase

Multi-tiered memory bank having different data buffer sizes...

Multidimensional network sorter integrated circuit

Multifunctional access devices, systems and methods

Multilevel semiconductor memory, write/read method...

Multimedia address generator

Multiple address sequence cache pre-fetching

Multiple address translations

Multiple changeable addressing mapping circuit

Multiple entry wavetable address cache to reduce accesses over a

Multiple page size address translation incorporating page...

Multiple page size address translation incorporating page...