Multi-sequence burst accessing for SDRAM

Details Multi-sequence burst accessing for SDRAM Multi-sequence burst accessing for SDRAM

2005-11-15

2005-11-15

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Generating a particular pattern/sequence of addresses

C711S005000, C711S219000, C711S220000, C710S029000

Reexamination Certificate

active

06965980

ABSTRACT:
Methods and apparatus for accessing memory locations in a memory device in different orders. In one implementation, a memory device includes: a memory array, including a plurality of memory locations divided into memory pages, where each memory location has a row address and a column address; a row decoder connected to the memory array for selecting a row address in the memory array; a column decoder connected to the memory array for selecting a column address in the memory array; and a multi-sequence address generator for generating addresses, where the multi-sequence address generator has a burst mode and in burst mode generates one of two or more burst sequences of addresses according to received burst parameters, and where each sequence has an index indicating the separation between two addresses in the sequence.

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