Verifying logic synthesizers
Verifying on-chip decoupling capacitance
Verifying one or more properties of a design using SAT-based...
Verifying proximity of ground metal to signal traces in an...
Verifying proximity of ground vias to signal vias in an...
Verilog to vital translator
Versatile multiplexer-structures in programmable logic using...
Versatile multiplexer-structures in programmable logic using...
Vertex based layout pattern (VEP): a method and apparatus...
Via enclosure rule check in a multi-wide object class design...
Via redundancy based on subnet timing information, target...
Via/BSM pattern optimization to reduce DC gradients and pin...
Video processing architecture definition by function graph...
Virtual component having a detachable...
Virtual data representation through selective bidirectional...
Virtual logic system for solving satisfiability problems...
Virtual path for interconnect fabric using bandwidth process
Virtual shape based parameterized cell
Virtual tree-based netlist model and method of delay...
Visual analysis and verification system using advanced tools