Timing-driven synthesis with area trade-off
Timing-insensitive glitch-free logic system and method
Toggle based application specific core methodology
Toggle equivalence preserving logic synthesis
Tool and method for improving the quality of board design...
Tool suite for the rapid development of advanced standard...
Tool suite for the rapid development of advanced standard...
Topological analysis based method for identifying state...
Topological global routing for automated IC package...
Topological global routing for automated IC package...
Topological vias route wherein the topological via does not...
Topology based wire shielding generation
Total overlay feed forward method for determination of...
Trace based method for design navigation
Trace delay error compensation
Trace equivalence identification through structural...
Trace equivalence identification through structural...
Tracing different states reached by a signal in a functional...
Tracing the change of state of a signal in a functional...
Transformation of graphs representing an electronic design...