Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-11-06
2003-05-06
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C703S014000
Reexamination Certificate
active
06560751
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to methods for manufacturing semiconductor devices, and more particularly to a method for determining the satisfaction of total overlay during the manufacture of semiconductor devices.
BACKGROUND OF THE INVENTION
The manufacture of semiconductor devices such as microprocessors involves the use of photolithography to impart detailed circuit patterns onto silicon dioxide layers disposed on a silicon wafer substrate. A typical microprocessor comprises many such layers, and is built up layer by layer, with each layer on the microprocessor potentially having a different circuit pattern.
The ultimate performance characteristics of the device are greatly affected by the overlay between adjacent layers in the device. One factor affecting overlay is the degree of misalignment between adjacent layers. If adjacent layers do not achieve the proper alignment tolerance, a large number of device defects can result, and the functionality of the device will be diminished.
An optical overlay measurement tool is often used to determine the degree of misalignment between adjacent layers during the manufacture of a semiconductor device. The tool can be adapted to use a number of commercially available techniques to generate alignment signals which indicate the position of a given layer relative to an adjacent layer or to the wafer substrate. The alignment signals are typically produced by optical measurement of alignment patterns. These alignment patterns typically consist of a series of marks which are etched onto a particular layer by photolithography such that the marks can be readily identified by the tool during the measurement process.
The process of measuring the degree of misalignment between two layers by means of alignment marks is known as registration. Registration involves comparing the position of a layer to that of a previous layer (or to the wafer substrate) by determining the misplacement between the alignment marks on the surfaces of the two layers. During registration, the degree of misalignment is determined by using the alignment marks to quantify the displacement between adjacent layers with respect to each of two orthogonal axes (e.g., the x-axis and the y-axis). The misalignment between the two layers is then typically taken as the larger of these two measurements.
While the procedure described above can control alignment errors that occur during the manufacture of the semiconductor device, it does not take into account other types of errors that can occur. For example, the total overlay between adjacent layers can also be affected by deviations in the size of the printed circuits on each of the adjacent layers as compared to the sizes of these circuits set forth in the device specifications. Moreover, while these and other parameters have been considered in the past in determining compliance with device specifications, they have been considered in isolation, such that the device is deemed defective if any one of these parameters individually falls outside of design tolerances. In fact, however, the present inventors have found that these parameters are interrelated, and that this interrelation must be taken into account for a truly accurate determination of compliance with device specifications and of the total overlay between two adjacent layers in the device.
There is thus a need in the art for a method for determining compliance with design specifications during the manufacture of an article, such as a semiconductor device, which takes into account the various parameters of the device affecting overlay as well as the interrelation between these parameters. These and other needs are met by the present invention, as hereinafter described.
SUMMARY OF THE INVENTION
In one aspect, the present invention relates to a method for determining compliance with design specifications in a product. In accordance with the method, a product is provided which is characterized by k parameters, k≧2, wherein, for n=1 to k, the n
th
parameter has a design specification value P
nDesign
and an actual value of P
nActual
, and wherein d
n
=P
nDesign
−P
nActual
. The value of
Δ
Actual
=
[
∑
n
=
1
k
d
n
2
]
1
/
2
is then determined. If &Dgr;
Actual
≦&Dgr;
Design
, where &Dgr;
Design
is the total design tolerance for the product, then the product is deemed to comply with design specifications. This methodology may be applied, for example, to the manufacture of a semiconductor device, where it may be implemented as part of an automated process.
In another aspect, the present invention relates to a method for determining compliance with product specifications in the manufacture of a semiconductor device. In accordance with the method, a semiconductor device is provided which comprises first and second adjacent layers, wherein the first and second layers have first and second circuit patterns disposed thereon, respectively. The value of &Dgr;
Actual
is then determined, wherein
&Dgr;
Actual
=[d
1
2
+d
2
2
+d
3
2
]{fraction (1/12)}
and wherein
d
1
=P
1Design
−P
1Actual
;
d
2
=P
2Design
−P
2Actual
;
d
3
is the misalignment between the first and second patterns;
P
1Design
is the dimension of the first pattern along a first axis as per design specifications;
P
1Actual
is the dimension of the first pattern along the first axis as actually measured;
P
2Design
is the dimension of the second pattern along the first axis as per design specifications; and
P
2Actual
is the dimension of the second pattern along the first axis as actually measured.
The value of &Dgr;
Actual
is preferably calculated after each layer is added to the semiconductor device, in which case the second layer is taken as the most recently added layer and the first layer is taken as the layer upon which the second layer is disposed. If &Dgr;
Actual
≦&Dgr;
Design
, where &Dgr;
Design
is the total design tolerance for each layer pair in the device, then the device may be passed onto the next processing step. If &Dgr;
Actual
>&Dgr;
Design
, the device may be either scrapped or reworked.
In still another aspect, the present invention relates to a method for manufacturing a multilayer semiconductor device. In accordance with the method, a substrate, such as a silicon wafer, is provided. A first layer having a first printed circuit pattern thereon is then deposited or formed on the substrate. Then, for n=2 to k, where k≧2, the following steps are performed for so long as &Dgr;
Actual
<n|n−1>≦&Dgr;
Design
, where &Dgr;
Actual
<n|n−1> is the total overlay between the nth and (n−1)th layers:
(a) an nth layer is deposited or formed on the substrate, and
(b) the value of
&Dgr;
Actual
<n|n−1
>=[d
1
2
+d
2
2
+d
3
2
]½
is determined, wherein
d
1
=P
n−1Design
−P
n−1Actual
,
d
2
=P
nDesign
−P
nActual
,
d
3
is the misalignment between the (n−1)th and the nth patterns,
P
n−1Design
is the dimension of the (n−1)th pattern along a first axis as per design specifications,
P
n−1Actual
is the dimension of the (n−1)th pattern along the first axis as actually measured,
P
nDesign
is the dimension of the nth pattern along the first axis as per design specifications,
P
nActual
is the dimension of the nth pattern along the nth axis as actually measured, and
&Dgr;
Design
is the total design tolerance established for the semiconductor device.
In the event that &Dgr;
Actual
<n|n−1>>&Dgr;
Design
for any layer pair, the device may be scrapped, or it may be reworked until &Dgr;
Actual
<n|n−1>≦&Dgr;
Design
, in which case the method is continued until n=k.
In yet another aspect, the present invention relates to a software program disposed in a tangible medium, and containing instructions adapted to implement any of the above described methods.
REFERENCES:
Dimyan Magid Y
Fortkort, Esq. John A.
Mayer Fortkort & Williams PC
Siek Vuthe
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