Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-12-14
2002-10-22
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C703S016000, C714S045000, C324S528000, C324S759030, C324S763010, C324S765010, C326S016000, C326S047000, C326S101000, C327S565000
Reexamination Certificate
active
06470480
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the electronic design of integrated circuits, and more specifically to a method and apparatus for the functional verification of a target integrated circuit design.
2. Related Art
Functional verification is one of the steps in the design of many integrated circuits. Functional verification generally refers to determining whether a design (“target design”) representing an integrated circuit performs a function it is designed for. In a typical design process, a designer identifies the functions to be performed and designs a circuit using high-level languages (e.g., VHDL language well known in the relevant arts) to perform the identified functions. An example of a function may be to generate a predetermined output data corresponding to a given input data. Tools available in the industry are typically used to generate a lower-level design (e.g., at gate-level) from the design specified in a high-level language. The higher level languages are generally more understandable to a user (human-being) while the lower level languages are closer in representation to the physical implementation.
Usually, the lower level design is evaluated against input data to generate output data. A determination of the accuracy of a functional design may be made based on the output data. The manner in which input data is generated and output data is used for determination of accuracy may depend on the specific type of verification environment. For example, in an emulation environment, the target design receives input data in a “real environment” usually having other components, whose operation can be relied on for accuracy. The target design is implemented to typically operate at least with these other components. By testing the target design in combination with these other components, functional verification of the target design can be performed. In general, a functional verification system operating in an emulation environment needs to generate output data values quickly such that the output data is available in a timely manner for the other components.
In contrast, in a simulation environment, a designer specifies pre-determined input data and evaluates the target design against the input data. The output data generated by the evaluation is examined to determine whether the design performs the desired functions. Once a designer is satisfied with a design, the data representing the design is sent for fabrication as an integrated circuit.
Accuracy in the functional verification is an important requirement in the design process for several reasons. For example, it is relatively less expensive to alter a circuit design prior to fabrication compared to re-designing and sending the design data for fabrication. In addition, it may require several weeks of time to redesign and complete fabrication again. Such levels of delays may be unacceptable, particularly in the high-technology markets where short design cycles are generally important.
In addition to accuracy, the verification step needs to scale well to the functional verification of integrated circuits of large sizes. That is, a verification systems needs to provide for verification of integrated circuit designs of large sizes. As is well known, an integrated circuit (semi-conductor chip) can include transistors of the order of a few millions, and the number has been increasing over time.
Furthermore, it is generally desirable that the verification step be completed quickly or with minimal internal computations. The speed of verification is particularly important in view of the increase in size and complexity of integrated circuits. To decrease the total design cycle time, it is desirable that the functional verification be completed quickly.
Co-pending U.S. Patent Application entitled, “Functional Verification of Integrated Circuit Designs”, Ser. No. 09/097,874, Filed: Jun. 15, 1998, now U.S. Pat. No. 6,138,266, describes some functional verification systems in which a target design is partitioned into many combinatorial logic blocks connected by sequential elements (e.g., flip-flops) and with appropriate dependencies. The state tables corresponding to the logic blocks are evaluated and stored in multiple random access storage devices (RASDs).
The output corresponding to each input combination is stored such that the output is retrieved from the corresponding RASD when the input combination is provided as a memory address to the RASD. For example, assuming a four input combinatorial logic and a RASD having four bits address bus, if the output the combinatorial logic is to be a 1 corresponding to an input of 1011, a ‘1’ is stored in the memory location corresponding to address 1011.
Cross-connects (XCONs) may interconnect the RASDs and enforce the dependencies which preserve the overall function of the target design. In general, the XCONs provide the outputs resulting from evaluation as memory addresses to RASDs. An XCON may be connected to multiple RASDs, and the XCON together with the connected RASDs may be referred to as a combinatorial logic output evaluator (CLOE).
In an approach described in the co-pending application noted above, each CLOE is connected to 16 other CLOEs (termed as neighbors). One of these CLOEs acts as a central CLOE to communicate with other groups of 16 CLOEs. In other words, if the output of a combinatorial logic evaluated in a first group and the output is to be provided as an input to a RASD in another group, the central CLOEs of the two groups may need to communicate to enable the necessary data transfer.
Such an approach may have several disadvantages. For example, the scheduling of evaluation of a combinatorial block may be undesirably complicated as the inputs may need to be communicated from several CLOEs and due to the ‘hierarchy’ in communication resulting from the central CLOE. Accordingly, the embodiments of the co-pending application may not be suitable in some environments.
Therefore, what is needed is a method and apparatus which enables the CLOE outputs to be communicated in an efficient manner such that the evaluations can be scheduled and performed quickly. In addition, the approach generally needs to allows for one or more of several related features such as tracing, verification of cycle based and non-cycle based designs, etc.
SUMMARY OF THE INVENTION
The present invention provides information on whether a signal has reached any/all of several possible states. Specifically, a variable is associated with the signal, and the variable contains sufficient number of states to indicate whether a signal has attained each possible state. For example, the signal may be binary signal with 0 and 1 as the possible values.
Accordingly, in one embodiment, a two bit variable may be chosen, with both bits being initialized to 0. The first bit may be set to 1 to indicate if a value of 0 is received for the signal, and the second bit may be set to 1 if a value of 1 is received for the signal. Thus, at the end of the functional verification, the two bits may be examined to determine whether the signal has been evaluated at all, reached 0, reached 1, or reached both states.
The signal may represent the output resulting from the evaluation of a combinatorial block, with many combinatorial blocks forming the target design sought to be verified. The combinatorial blocks may be grouped into multiple clusters, with the combinatorial blocks within a cluster being evaluated in parallel. The outputs of all the evaluated combinatorial blocks may be provided on a bus, with each output being provided on a pre-specified position.
A trace controller may receive multiple bits and a cluster identifier identifying the specific cluster to which the bits relate to. The variable may be stored at an address equal to the cluster number such that the variable can be readily accessed based on the cluster number.
An aspect of the present invention provides information as to whether a signal has reached both 0 and 1 states as a corresponding variable is updated to r
Broukhis Leonid Alexander
Ganesan Subbu
Narayanaswamy Ramesh
Nixon Ian Michael
Kik Phallaka
Law Firm of Naren Thappeta
Siek Vuthe
Tharas Systems Inc.
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