Toggle equivalence preserving logic synthesis

Details Toggle equivalence preserving logic synthesis Toggle equivalence preserving logic synthesis

2006-09-25

2009-10-06

Rossoshek, Helen (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07600211

ABSTRACT:
A method of synthesis of a second circuit (N2) that is toggle equivalent to a first circuit (N1), comprising building up N2in topological order, starting from the input side of N2, by producing a sequence of subcircuit designs N2(1)through N2(k), such that output toggling of circuit N1implies output toggling of subcircuit N2(1)for every i=1, . . , k; and output toggling of N2(j)strictly implies output toggling of N2(i)if i<j.

REFERENCES:
patent: 5991524 (1999-11-01), Belkhale et al.
patent: 6397170 (2002-05-01), Dean et al.
patent: 6983435 (2006-01-01), Baumgartner et al.
patent: 7100143 (2006-08-01), Teig et al.
patent: 7137084 (2006-11-01), Chen et al.
patent: 7215142 (2007-05-01), Fairbanks
patent: 7240311 (2007-07-01), Lai et al.
patent: 7360185 (2008-04-01), Baumgarter et al.
patent: 7373618 (2008-05-01), Khoo et al.
patent: 7380226 (2008-05-01), Goldberg
Goldberg et al.; “Toggle Equivalence Preserving (TEP) Logic Optimization”; Aug. 29-31, 2007; Digital System Design Architectures, Methods and Tools, 2007. DSD 2007. 10th Euromicro Conference on; pp. 271-279.
Goldberg et al.; “Using SAT for combinational equivalence checking”; Mar. 13-16, 2001; Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings; pp. 114-121.
Mishchenko et al.; “Improvements to Combination Equivalence Checking”; Nov. 2006; Computer-Aided Design, 2006. ICCAD '06. IEEE/ACM International Conference on; pp. 836-843.
Eugene Goldberg, “On Equivalence Checking and Logic Synthesis of Circuits with a Common Specification,” GLSVLSI'05, Apr. 17-19, 2005, Chicago, IL, pp. 102-107.
E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton and A. L. Sangiovanni-Vincentelli, “SIS: A System for Sequential Circuit Synthesis,” Tech. Rep. UCB/ERL M92/41, Electronics Research Lab, Univ. of California, Berkeley, CA, May 4, 1992.
S. Yamashita, H. Sawada and A. Nagoya, “A New Method to Express Functional Permissibilities for LUT Based FPGAs and Its Applications,” in Proc. of IEEE International Conference on Computer-Aided Design, pp. 254-261, Nov. 1996.
U.S. Appl. No. 11/027,085, entitled, “Method and Apparatus to Perform Logic Synthesis Preserving High-Level Specification”, filed Dec. 29, 2004, invented by E. Goldberg.
S. Sinha and R. K. Brayton, “Implementation and Use of SPFDs in Optimizing Boolean Networks,” in Proc. of IEEE International Conference an Computer-Aided Design, pp. 103-110, Nov. 1998.
R. K. Brayton and C. McMullen, “The Decomposition and Factorization of Boolean Expressions,” in Proc. of IEEE International Symposium on Circuits and Systems, pp. 49-54, May 1982.
J. Vasudevamurthy and J. Rajski, “A Method for Concurrent Decomposition and Factorization of Boolean Expressions,” in Proc. of IEEE International Conference on Computer-Aided Design, pp. 510-513, Nov. 1990.
H. Savoj and R. K. Brayton, “The Use of Observability and External Don't Cares for the Simplification of Multi-Level Networks,” in Proc. of ACM/IEEE Design Automation Conference, pp. 297-301, Jun. 1990.
H. Savoj, R. K. Brayton and H. J. Touati, “Extracting Local Don't Cares for Network Optimization,” in Proc. of IEEE International Conference on Computer-Aided Design, pp. 514-517, Nov. 1991.
H. Savoj, “Don't Cares in Multi-Level Network Optimization,” PhD thesis, University of California Berkeley, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, CA, May 1992.
S. P. Khatri, S. Sinha, R. K. Brayton and A. L. Sangiovanni-Vincentelli, “SPFD-Based Wire Removal in Standard-Cell and Network-of-PLA Circuits,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, No. 7, pp. 1020-1030, Jul. 2004.
S. Sinha, A. Kuehlmann and R. K. Brayton, “Sequential SPFDs,” in Proc. of IEEE International Conference on Computer-Aided Design, pp. 84-90, Nov. 2001.
S. Sinha, A. Mishchenko and R. K. Brayton, “Topologically Constrained Logic Synthesis,” in Proc. of IEEE International Conference on Computer-Aided Design, pp. 679-686, Nov. 2002.
R. E. Bryant, “Graph-Based Algorithms for Boolean Function Manipulation,” IEEE Trans. on Computers, vol. C-35, No. 8, pp. 677-691, Aug. 1986.
F. Somenzi, “Cudd: Cu Decision Diagram Package Release 2.4.1,” Dept. of Electrical and Computer Engineering, Univ. of Colorado at Boulder, downloaded Apr. 27, 2006. Available online at http://vlsi.colorado.edu/˜fabio/CUDD/.

Affiliated with

Also associated with

Rating

Toggle equivalence preserving logic synthesis does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Toggle equivalence preserving logic synthesis, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Toggle equivalence preserving logic synthesis will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4089483