Timing-driven synthesis with area trade-off

Details Timing-driven synthesis with area trade-off Timing-driven synthesis with area trade-off

2007-07-17

2007-07-17

Lin, Sun James (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

10849534

ABSTRACT:
An embodiment of the invention is a logic minimization method that provides improved user design performance without a substantial increase in user design area. Alternate factorizations are determined for portions of the user design. For each factorization, a delay metric is computed. The user design is optimized by selecting factorizations based on a balance of performance and area considerations. The optimized design is then mapped to the hardware architecture of the programmable device. A first portion of the user design is mapped to maximize performance, while a second portion of the user design is mapped to minimize area. The first portion of the user design includes a set of data paths each having a delay metric above a delay threshold. The delay metric can be derived from a unit delay computation or from timing analysis.

REFERENCES:
Vuillod et al., “Generalized Matching from Theory to Application”, Nov. 1997, IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers., pp. 13-21.
Benini et al., “Iterative Remapping for Logic Circuits”, Oct. 1998, IEEE Teansactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, iss. 10, pp. 948-964.
Brayton, Robert K. et al.; “MIS: A Multiple-Level Logic Optimization System”; 1987,IEEE Transactions on Computer-Aided Design; vol. CAD-6, No. 6, pp. 1062-1081.
Cong, Jason et al.; “Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping”; 1995,Proceedings of the ACM/SIGDA International Symposium on FPGAs, Monterey, California, pp. 68-74.
Sentovich, Ellen M.. et al.; “SIS: A System for Sequential Circuit Synthesis”; 1992,Electronic Research Laboratorium Memorandum No. UCB/ERL M92/41, pp. 1-45.
van Antwerpen et al.; “Register Retiming Technique”; U.S. Appl. No. 10/446,650, filed May 27, 2003.

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