Generating components on a programmable device using a...
Generating components on a programmable device using a...
Generating constraint preserving testcases in the presence...
Generating cores using secure scripts
Generating fast logic simulation models for a PLD design...
Generating hardware interfaces for designs specified in a...
Generating interface adjustment signals in a...
Generating mask layout data for simulation of lithographic...
Generating mask patterns for alternating phase-shift mask...
Generating optimized and secure IP cores
Generating self-checking test cases from a reduced case...
Generating self-checking test cases from a reduced case...
Generating standard delay format files with conditional path...
Generation of a circuit design from a command language...
Generation of a hardware interface for a software procedure
Generation of a specification of a network packet processor
Generation of a specification of a processor of network packets
Generation of clock gating function for synchronous circuit
Generation of design views having consistent input/output...
Generation of engineering change order (ECO) constraints for...